Espressif ESP32 Technical Reference Manual page 678

30 ULP Coprocessor (ULP)
1
Master Slave Address W
Slave
Note:
The RTC_I2C peripheral samples the SDA signals on the falling edge of SCL. If the slave changes SDA in less
than 0.38 microseconds, the master will receive incorrect data.
The byte received from the slave is stored into the R0 register.
30.6.2.2 I2C_WR - Write a Single Byte
The I2C_WR instruction performs the following I²C transaction (see Figure 30-22):
1. Master generates a START condition.
2. Master sends slave address, with r/w bit set to 0 ("write"). Slave address is obtained from
SENS_I2C_SLAVE_ADDRn, where
3. Slave generates ACK.
4. Master sends slave register address (given as an argument to the I2C_WR instruction).
5. Slave generates ACK.
6. Master generates a repeated START condition.
7. Master sends slave address, with r/w bit set to 0 ("write").
8. Master sends one byte of data.
9. Slave generates ACK.
10. Master generates a STOP condition.
1
Master Slave Address W
Slave
30.6.2.3 Detecting Error Conditions
ULP I2C_RD and I2C_WR instructions will not report error conditions, such as a NACK from a slave, via ULP
registers. Instead, applications can query specific bits in the
transaction was successful. To enable checking for specific communication events, their corresponding bits
should be set in register RTC_I2C_INT_EN_REG. Note that the bit map is shifted by 1. If a specific
communication event is detected and set in register RTC_I2C_INT_ST_REG, it can then be cleared using
RTC_I2C_INT_CLR_REG.
Espressif Systems
2 3 4
Reg Address
Figure 30-21. I²C Read Operation
n is given as an argument to the
2 3 4
Reg Address
Figure 30-22. I²C Write Operation
Submit Documentation Feedback
5 6
7
Slave Address R
I2C_WR
5 6 7
Slave Address W
RTC_I2C_INT_ST_REG
678
8 9 10
Data
instruction.
8 9 10
Data
register to determine if the
ESP32 TRM (Version 5.2)