Espressif ESP32 Technical Reference Manual page 619

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27 Memory Management and Protection Units (MMU, MPU)

* The configuration entries for address range 0x4000_0000 ~ 0x403F_FFFF are implemented and doc-

umented as if it were a full 4 MB address range, but it is not accessible as such. Instead, the address range

0x4000_0000 ~ 0x400C_1FFF accesses on-chip memory. This means that some of the configuration entries

will not be used.

External Flash

For flash, the relationships among entry numbers, virtual memory ranges, and PIDs are detailed in Tables

and 27-11, which for every memory region and PID combination specify the first MMU entry governing the

mapping. This number refers to the MMU entry governing the very first page; the entire region is described by

the amount of pages specified in the 'count' column.

These two tables are essentially the same, with the sole difference being that the APP_CPU entry numbers are

2048 higher than the corresponding PRO_CPU numbers. Note that memory regions V Addr

only accessible using PID 0 and 1, while V Addr

As these tables show, virtual address V Addr

Espressif Systems

Table 27-9. Virtual Address for External Memory

Boundary address

can only be accessed by PID 2 ~ 7.

Table 27-10. MMU Entry Numbers for PRO_CPU

Table 27-11. MMU Entry Numbers for APP_CPU

can only be used by processes with a PID of 0 or 1. There

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First MMU entry for PID

First MMU entry for PID

Page quantity

ESP32 TRM (Version 5.2)

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