Espressif ESP32 Technical Reference Manual page 563

21 Two-wire Automotive Interface (TWAI)
of 5, only data bytes 1 to 5 will contain valid payload data for the CPU to read.
21.5.5 Receive FIFO and Data Overruns
The Receive FIFO is a 64-byte internal buffer used to store received messages in First In First Out order. A single
received message can occupy between 3 to 13-bytes of space in the Receive FIFO, and their byte layout is
identical to the register layout of the Receive Buffer registers. The Receive Buffer registers are mapped to the
bytes of the first message in the Receive FIFO. When the TWAI controller receives a message, it will increment
the value of TWAI_RX_MESSAGE_COUNTER up to a maximum of 64. If there is adequate space in the Receive
FIFO, the message contents will be written into the Receive FIFO. Once a message has been read from the
Receive Buffer, the TWAI_RELEASE_BUF bit should be set. This will decrement TWAI_RX_MESSAGE_COUNTER
and free the space occupied by the first message in the Receive FIFO. The Receive Buffer will then map to the
next message in the Receive FIFO.
When the TWAI controller receives a message, but the Receive FIFO lacks the adequate free space to store
the received message in its entirety (either due to the message contents being larger than the free space
in the Receive FIFO, or the Receive FIFO being completely full), the Receive FIFO will internally mark overrun
messages as invalid. Subsequent overrun messages will still increment the TWAI_RX_MESSAGE_COUNTER up
to a maximum of 64.
To clear an overrun Receive FIFO, the TWAI_RELEASE_BUF must be called repeatedly called until TWAI_RX_
MESSAGE_COUNTER is 0. This has the effect of freeing all valid messages in the Receive FIFO and clearing all
overrun messages.
21.5.6 Acceptance Filter
The Acceptance Filter allows the TWAI controller to filter out received messages based on their ID (and optionally
their first data byte and frame type). Only accepted messages are passed on to the Receive FIFO. The use of
Acceptance Filters allows for a more lightweight operation of the TWAI controller (e.g., less use of Receive FIFO,
fewer Receive Interrupts) due to the TWAI Controller only needing to handle a subset of messages.
The Acceptance Filter configuration registers can only be accessed whilst the TWAI controller is in Reset
Mode, due to those registers sharing the same address space as the Transmit Buffer and Receive Buffer regis-
ters.
The registers consist of a 32-bit Acceptance Code Value and a 32-bit Acceptance Mask Value. The Code value
specifies a bit pattern in which each filtered bit of the message must match in order for the message to be
accepted. The Mask value is able to mask out certain bits of the Code value (i.e., set as "Don't Care" bits).
Each filtered bit of the message must either match the acceptance code or be masked in order for the message
to be accepted, as demonstrated in Figure 21-7.
The TWAI Controller Acceptance Filter allows the 32-bit Code and Mask values to either define a single filter
(i.e., Single Filter Mode), or two filters (i.e., Dual Filter Mode). How the Acceptance Filter interprets the 32-bit
code and mask values is dependent on whether Single Filter Mode is enabled, and the received message (i.e.,
SFF or EFF).
Figure 21-7. Acceptance Filter
Espressif Systems 563 ESP32 TRM (Version 5.2)
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