Espressif ESP32 Technical Reference Manual page 543

20 eFuse Controller
31
0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT_ST The masked interrupt status bit for the
rupt. (RO)
EFUSE_READ_DONE_INT_ST The masked interrupt status bit for the
terrupt. (RO)
31
0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT_ENA The interrupt enable bit for the
(R/W)
EFUSE_READ_DONE_INT_ENA The interrupt enable bit for the
(R/W)
31
0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT_CLR Set this bit to clear the
EFUSE_READ_DONE_INT_CLR Set this bit to clear the
Espressif Systems
Register 20.25. EFUSE_INT_ST_REG (0x10c)
0 0 0 0 0 0 0 0
Register 20.26. EFUSE_INT_ENA_REG (0x110)
0 0 0 0 0 0 0 0
Register 20.27. EFUSE_INT_CLR_REG (0x114)
0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT
0 0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT
EFUSE_READ_DONE_INT
0 0 0 0 0 0 0 0
EFUSE_PGM_DONE_INT
EFUSE_READ_DONE_INT
543
2 1
0 0 0 0 0 0 0 0
inter-
EFUSE_READ_DONE_INT
2 1
0 0 0 0 0 0 0 0
interrupt.
interrupt.
2 1
0 0 0 0 0 0 0 0
interrupt. (WO)
interrupt. (WO)
ESP32 TRM (Version 5.2)
0
0 Reset
in-
0
0
Reset
0
0 Reset