Address Match Interrupt; Watchdog Timer - Renesas M16C Series User Manual

M30240 Group

1.2.15 Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents
match the program counter value. Two address match interrupts can be set, each of which can be
enabled and disabled by an address match interrupt enable bit. Address match interrupts are not
affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.20 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4
Address match interrupt register i (i = 0, 1)
(b23) (b19)
b7 b3
Figure 1.20: Address match interrupt-related registers

1.2.16 Watchdog Timer

The watchdog timer has the function of detecting when the program is out of control. The watchdog timer
is a 15-bit counter that decrements using the clock derived by dividing the internal clock Φ using the
prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. Bit
7 of the watchdog timer control register (address 000F
128). Table 1.13 shows the periodic table for the watchdog timer.
Table 1.13: Watchdog timer periodic table (f(X
CM06 CM17
0 0
0 0
0 1
0 1
1 Invalid
Note: The watchdog timer's period is subject to some error due to the prescaler.
Rev.1.00 Sep 24, 2003 Page 36 of 360
b3 b2 b1 b0
Symbol Address
AIER 0009
Bit symbol
Address match interrupt 0
AIER0
enable bit
AIER1 Address match interrupt 1
enable bit
Nothing is assigned.
Write 0 when writing to these bits. If read, the value is indeterminate.
(b16) (b15) (b8)
b0 b7 b0 b7
Function
Address setting register for address match interrupt
Nothing is assigned.
Write 0 when writing to these bits. If read, the value is indeterminate.
Internal clock Φ
CM16
0 12MHz
1 6MHz
0 3MHz
1 0.75MHz
Invalid 1.5MHz
When reset
XXXXXX00
16 2
Bit name Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Symbol Address
b0
RMAD0 0012 to 0010
16 16
RMAD1 0016 to 0014
16 16
Values that can be set
00000 to FFFFF
16
) selects the prescaler division ratio (by 16 or
16
)=12MHz)
IN
WDC7
0
1
0
1
0
1
0
1
0
1
Address Match Interrupt
R W
When reset
X00000
16
X00000
16
R W
16
Period (Note)
Approx. 43.7ms
Approx. 349.5ms
Approx. 87.4ms
Approx. 699.1ms
Approx. 174.8ms
Approx. 1.40s
Approx. 699.1ms
Approx. 5.59s
Approx. 349.5ms
Approx. 2.80s