Address Match Interrupt - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Address Match Interrupt

An address match interrupt request is generated immediately before executing the instruction at the
address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER register's AIER0 and AIER1 bits and the AIER2 register's AIER20 and AIER21 bits
to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the
instruction being executed (refer to "Saving Registers"). (The value of the PC that is saved to the stack area
is not the correct return address.) Therefore, follow one of the methods described below to return from the
address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 1.10.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Note that when using the external bus in 8-bit width, no address match interrupts can be used for external
areas. Table 1.10.7 shows the relationship between address match interrupt sources and associated registers.
Figure 1.10.14 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 1.10.6 Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted
Instruction at address indicated by RMADi register
• 16-bit operation code
• Instruction shown below among 8-bit operation code instructions
ADD.B:S #IMM8,dest
OR.B:S #IMM8,dest
STNZ.B:S #IMM8,dest
CMP.B:S #IMM8,dest
JMPS #IMM8
MOV.B:S #IMM,dest (However, dest = A0 or A1)
• Instructions other than the above
Value of PC that is saved to stack area: Refer to "Saving Registers".
Table 1.10.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit
Address match interrupt 0 AIER0
Address match interrupt 1 AIER1
Address match interrupt 2 AIER20
Address match interrupt 3 AIER21
Rev.1.00 2003.05.30 page 83
SUB.B:S #IMM8,dest AND.B:S
MOV.B:S #IMM8,dest STZ.B:S
STZX.B:S #IMM81,#IMM82,dest
PUSHM src POPM dest
JSRS #IMM8
Value at PC that is saved to stack area
• Address indicated by RMADi
register + 2
#IMM8,dest
#IMM8,dest
• Address indicated by RMADi
register + 1
Address match interrupt register
RMAD0
RMAD1
RMAD2
RMAD3
Interrupts