Motorola PowerQUICC II MPC8280 Series Reference Manual page 164

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x1132E Reserved
0x11330 FCC2 event register (FCCE2)
0x11332 Reserved
0x11334 FCC2 mask register (FCCM2)
0x11336 Reserved
0x11338 FCC2 status register (FCCS2)
0x11339 Reserved
0x1133C FCC2 transmit internal rate registers for PHY0
(FTIRR2_PHY0)
0x1133D FCC2 transmit internal rate registers for PHY1
(FTIRR2_PHY1)
0x11133E FCC2 transmit internal rate registers for PHY2
(FTIRR2_PHY2)
0x1133F FCC2 transmit internal rate registers for PHY3
(FTIRR2_PHY3)
0x11340 FCC3 general mode register (GFMR3)
0x11344 FCC3 protocol-specific mode register (FPSMR3)
0x11348 FCC3 transmit on-demand register (FTODR3)
0x1134A Reserved
0x1134C FCC3 data synchronization register (FDSR3)
0x1134E Reserved
3-12
Freescale Semiconductor, Inc.
Register
FCC3
MPC8280 PowerQUICC II Family Reference Manual
For More Information On This Product,
Go to: www.freescale.com
R/W Size Reset
— 16 bits —
R/W 16 bits 0x0000_0000 31.13.3/-94
— 16 bits —
R/W 16 bits 0x0000_0000 31.13.3/-94
— 16 bits —
R 16 bits 0x00
— 24 bits —
R/W 8 bits 0x00
R/W 8 bits 0x00
R/W 8 bits 0x00
R/W 8 bits 0x00
R/W 32 bits 0x0000_0000 30.2/-3
R/W 32 bits 0x0000_0000 31.13.2/-91
R/W 16 bits 0x0000
— 16 bits —
R/W 16 bits 0x7E7E
— 16 bits —
Section/Page
—
(ATM)
36.18.2/-23
(Ethernet)
37.9/-14
(HDLC)
—
(ATM)
36.18.2/-23
(Ethernet)
37.9/-14
(HDLC)
—
37.10/-16
(HDLC)
—
31.15.1.4/-99
(ATM)
34.4.2.1.2/-24
(IMA)
(ATM)
34.4.2.1.1/-24
(IMA)
36.18.1/-21
(Ethernet)
37.6/-8 (HDLC)
30.5/-9
—
30.4/-8
—
MOTOROLA