Motorola PowerQUICC II MPC8280 Series Reference Manual page 169

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x11500 TC general status register (TCGSR)
0x11502 TC general event register (TCGER)
0x115F0 BRG5 configuration register (BRGC5)
0x115F4 BRG6 configuration register (BRGC6)
0x1115F8 BRG7 configuration register (BRGC7)
0x115FC BRG8 configuration register (BRGC8)
0x11600– Reserved
0x1185F
2
0x11860 I C mode register (I2MOD)
0x11861 Reserved
2
0x11864 I C address register (I2ADD)
0x11865 Reserved
2
0x11868 I C BRG register (I2BRG)
0x11869 Reserved
2
0x1186C I C command register (I2COM)
0x1186D Reserved
2
0x11870 I C event register (I2CER)
0x11871 Reserved
2
0x11874 I C mask register (I2CMR)
0x11875– Reserved
0x119BF
0x119C0 Communications processor command register (CPCR) R/W
0x119C4 CP configuration register (RCCR)
0x119C8– Reserved
0x119D5
0x119D6 CP timers event register (RTER)
0x119DA CP timers mask register (RTMR)
0x119DC CP time-stamp timer control register (RTSCR)
0x119DE Reserved
MOTOROLA
Freescale Semiconductor, Inc.
Register
TC Layer—General
1
1
BRGs 5–8
2
I
Communications Processor
Chapter 3. Memory Map
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Go to: www.freescale.com
R/W Size
1
R 16 bits
R/W 16 bits
R/W 32 bits 0x0000_0000 17.1/-2
R/W 32 bits 0x0000_0000
R/W 32 bits 0x0000_0000
R/W 32 bits 0x0000_0000
— 608 bytes
C
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 24 bits
R/W 8 bits
— 315 bytes
32 bits 0x0000_0000 14.4.1/-12
R/W 32 bits 0x0000_0000 14.3.7/-9
— 12 bytes
R/W 16 bits 0x0000_0000 14.6.4/-27
R/W 16 bits 0x0000_0000
— 16 bits
R/W 16 bits
Reset Section/Page
0x0000 35.4.2.2/-12
0x0000 35.4.2.1/-11
— —
0x00 40.4.1/-6
— —
0x00 40.4.2/-7
— —
0x00 40.4.3/-8
— —
0x00 40.4.5/-9
— —
0x00 40.4.4/-8
— —
0x00 40.4.4/-8
— —
— —
0x0000 14.3.8/-10
—
3-17