Boot Sequence - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Table 10-2. Flash Option Register Bit Definitions (continued)

10.3.3 Boot sequence

At power up, the on-chip regulator holds the system in a POR state until the input supply

is above the POR threshold. The system continues to be held in this static state until the

internally regulated supplies have reached a safe operating voltage as determined by the

LVD. The Mode Controller reset logic then controls a sequence to exit reset.

1. A system reset is held on internal logic, the RESET pin is driven out low, and the

MCG is enabled in its default clocking mode.

2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus

Clocks that do not have clock gate control).

3. The system reset on internal logic continues to be held, but the Flash Controller is

released from reset and begins initialization operation while the Mode Control logic

continues to drive the RESET pin out low for a count of ~128 Bus Clock cycles.

4. The RESET pin is released, but the system reset of internal logic continues to be held

until the Flash Controller finishes initialization. .

5. When Flash Initialization completes, the RESET pin is observed. If RESET

continues to be asserted (an indication of a slow rise time on the RESET pin or

external drive in low), the system continues to be held in reset. Once the RESET pin

is detected high, the system is released from reset.

6. At release of system reset, clocking is switched to a slow clock if the

FOPT[LPBOOT] field in the Flash Memory module is configured for Low Power

Reserved for future expansion.

Control the reset value of OUTDIVx values in SIM_CLKDIV1 register. Larger divide value

selections produce lower average power consumption during POR, VLLSx recoveries and

reset sequencing and after reset exit.

Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at

reset exit for higher divide values that produce lower power consumption at reset

• Core and system clock divider (OUTDIV1) and fast peripheral clock divider

(OUTDIV2) are 0x7 (divide by 8)

• Flash/Bus clock divider (OUTDIV4) are 0xF (divide by 16)

Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at

reset exit for higher frequency values that produce faster operating frequencies at

• Core and system clock divider (OUTDIV1) and fast peripheral clock divider

(OUTDIV2) are 0x0 (divide by 1

• Flash/Bus clock divider (OUTDIV4) are 0x1 (divide by 2)

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.