Chapter 5 Memory Map; System Memory Map - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

5.1 Introduction

This chip contains both Flash and RAM memories and memory-mapped peripherals

which are located in one contiguous memory space. The ARM M4 core supports both

memory sizes present.

• 256KB Flash memory

The following table shows the high-level device memory map. This map provides the

complete architectural address space definition for the various sections. Based on the

physical sizes of the memories and peripherals, the actual address regions used may be

The system memory map includes multiple alias address spaces that are intended for

specific purposes. There are two aliased address spaces that are mapped into the ICode

regions (address < 0x2000_0000) for code sections that are normally located in the

system region of the memory map. However, two subsets of this space are aliased so they

appear in the ICode region. This enables the instructions mapped into this space to be

executed with maximum performance.

There is an aliased region that maps a system address space to the Program flash section.

The Flash region aliasing is specifically intended for references to read-only data

coefficients in the flash while still preserving a full Harvard memory organization in the

processor core supporting concurrent instruction fetches (for example, from RAM) and

data accesses (from flash via the aliased space).

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015