Table of Contents
Advertisement
8 or above
43.4.54 Rx FIFO structure
When the CAN_MCR[RFEN] bit is set, the memory area from 0x80 to 0xDC (which is
normally occupied by MBs 0–5) is used by the reception FIFO engine.
The region 0x80-0x8C contains the output of the FIFO which must be read by the CPU as
a message buffer. This output contains the oldest message that has been received but not
yet read. The region 0x90-0xDC is reserved for internal use of the FIFO engine.
An additional memory area, which starts at 0xE0 and may extend up to 0x17C (normally
occupied by MBs 6–15) depending on the CAN_CTRL2[RFFN] field setting, contains
the ID filter table (configurable from 8 to 40 table elements) that specifies filtering
criteria for accepting frames into the FIFO.
Out of reset, the ID filter table flexible memory area defaults to 0xE0 and extends only to
0xFC, which corresponds to MBs 6 to 7 for RFFN = 0, for backward compatibility with
previous versions of FlexCAN.
The following shows the Rx FIFO data structure.
31
28
0x80
IDHIT
0x84
0x88
Data byte 0
0x8C
Data byte 4
0x90
to
0xDC
0xE0
0xE4
0xE8
to
0x2D4
Freescale Semiconductor, Inc.
Table 43-108. DATA BYTEs validity (continued)
DLC
5
6
7
Table 43-109. Rx FIFO structure
24
23
22
21
20
SRR
IDE RTR
ID standard
Data byte 1
Data byte 5
ID filter table element 0
ID filter table element 1
ID filter table elements 2 to 125
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 43 Flex Controller Area Network (FlexCAN)
Valid DATA BYTEs
DATA BYTE 0 to 4
DATA BYTE 0 to 5
DATA BYTE 0 to 6
DATA BYTE 0 to 7
19
18
17
16
15
DLC
Data byte 2
Data byte 6
Reserved
8
7
TIME STAMP
ID extended
Data byte 3
Data byte 7
1127
0
Advertisement
Table of Contents
