Dma Channels With Periodic Triggering Capability - NXP Semiconductors freescale KV4 Series Reference Manual

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DMAMUX_CHCFGn field descriptions (continued)

Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the

specified source to the DMA channel. (Normal mode)

Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger

DMA Channel Source (Slot)

Specifies which DMA source, if any, is routed to a particular DMA channel. See the chip-specific

DMAMUX information for details about the peripherals and their slot numbers.

22.5 Functional description

The primary purpose of the DMAMUX is to provide flexibility in the system's use of the

available DMA channels.

As such, configuration of the DMAMUX is intended to be a static procedure done during

execution of the system boot code. However, if the procedure outlined in

configuring sources

is followed, the configuration of the DMAMUX may be changed

during the normal operation of the system.

Functionally, the DMAMUX channels may be divided into two classes:

• Channels that implement the normal routing functionality plus periodic triggering

• Channels that implement only the normal routing functionality

22.5.1 DMA channels with periodic triggering capability

Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a

special periodic triggering capability that can be used to provide an automatic mechanism

to transmit bytes, frames, or packets at fixed intervals without the need for processor

intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the

configuration of the periodic triggering interval is done via configuration registers in the

PIT. See the section on periodic interrupt timer for more information on this topic.

Because of the dynamic nature of the system (due to DMA

channel priorities, bus arbitration, interrupt service routine

lengths, etc.), the number of clock cycles between a trigger and

the actual DMA transfer cannot be guaranteed.

Freescale Semiconductor, Inc.

Chapter 22 Direct memory access multiplexer (DMAMUX)

KV4x Reference Manual, Rev. 2, 02/2015

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