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Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Number of peripheral bridges
This device contains one peripheral bridge AIPS-Lite with registers.
21.2 Memory map
The peripheral bridge is used to access the registers of most of the modules on this
device. See
Peripheral Memory Map
for the memory slot assignment of each module.
21.3 PACR registers
The single peripheral bridge supports up to 128 peripherals each assigned to a PACRx
field within the PACRA-PACRP registers. However, fewer peripherals are supported on
this device. See
Peripheral Memory Map
for details of the peripheral slot assignments for
this device. Unused PACRx fields are reserved.
21.4 AIPS_Lite PACRE-P register reset values
The AIPSx_PACRE-P register reset values depend on the availability of a module on the
chip. For each populated slot in slots 32-127 in
Peripheral Bridge 0 (AIPS-Lite 0)
Memory
Map, the corresponding module's PACR[32:127] field resets to 0x4.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
337
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