Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr) - ST STM32F205 series Reference Manual

Reset and clock control (RCC)
Bit 0 LSIRDYF: LSI ready interrupt flag
5.3.5

RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
OTGHS
RST
Reserved
rw
15 14 13 12
CRCRS
T
Reserved
rw
Bits 31:30
Bit 29 OTGHSRST: USB OTG HS module reset
Bits 28:26
Bit 25 ETHMACRST: Ethernet MAC reset
Bits 24:23
Bit 22 DMA2RST: DMA2 reset
Bit 21 DMA1RST: DMA2 reset
Bits 20:13
Bit 12 CRCRST: CRC reset
Bits 11:9
104/1378
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
27 26 25
ETHMAC
RST
Reserved
rw
11 10 9
Reserved
Reserved, always read as 0.
Set and cleared by software.
0: does not reset the USB OTG HS module
1: resets the USB OTG HS module
Reserved, always read as 0.
Set and cleared by software.
0: does not reset Ethernet MAC
1: resets Ethernet MAC
Reserved, always read as 0
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Reserved, always read as 0.
Set and cleared by software.
0: does not reset CRC
1: resets CRC
Reserved, always read as 0
24 23 22
DMA2 DMA1
RST
Reserved
rw
8 7 6
GPIOI GPIOH GPIOGG GPIOF
RST RST RST
rw rw rw
RM0033 Rev 8
21 20 19 18
RST
Reserved
rw
5 4 3 2
GPIOE GPIOD GPIOC
RST RST RST RST
rw rw rw rw
RM0033
17 16
1 0
GPIOB GPIOA
RST RST
rw rw