Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr) - ST STM32F410 Reference Manual

RM0401
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
5.3.5

RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
RNG
Res. Res. Res.
RST
rw
15 14 13 12
Res. Res. Res. CRCRST
rw
Bit 31 RNGRST: RNG reset
Bits 30:23 Reserved, must be kept at reset value.
Bit 22 DMA2RST: DMA2 reset
Bit 21 DMA1RST: DMA1 reset
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Bits 11:8 Reserved, must be kept at reset value.
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
Set and cleared by software.
0: does not reset RNG
1: resets RNG
Set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Set and cleared by software.
0: does not reset DMA1
1: resets DMA1
Set and cleared by software.
0: does not reset CRC
1: resets CRC
24 23 22
DMA2 DMA1
Res. Res.
RST
rw
8 7 6
GPIOH
Res. Res. Res.
RST
rw
RM0401 Rev 3
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res.
RST
rw
5 4 3 2
GPIOC
Res. Res.
RST
rw
17 16
Res. Res.
1 0
GPIOB GPIOA
RST RST
rw rw
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