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Embedded Flash memory (FLASH)
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 C2SWDBGEN: CPU2 software debug enable
Bit 1 HDPADIS: Flash user hide protection area access disable
Bit 0 PRIVMODE: FLASH privileged mode enable
4.10.3
FLASH key register (FLASH_KEYR)
Address offset: 0x008
Reset value: 0x0000 0000
s
31
30
29
w
w
w
15
14
13
w
w
w
Bits 31:0 KEY[31:0]: Flash key
4.10.4
FLASH option key register (FLASH_OPTKEYR)
Address offset: 0x00C
Reset value: 0x0000 0000
s
31
30
29
w
w
w
15
14
13
w
w
w
130/1461
This bit is set and reset by software.
When HDPAD = 0 (hide protection area enabled), the CPU2 software debug is disabled after
a system reset.
When HDPAD = 1 (hide protection area disabled), the CPU2 software debug is enabled after
a system reset.
0: CPU2 debug access disabled
1: CPU2 debug access enabled (when also enabled in DDS)
This bit is set by software and is only reset by hardware on a system reset.
0: User Flash hide protection area access enabled
1: User Flash hide protection area access disabled
This bit is set and reset by software.
0: FLASH register access privileged mode disabled
1: FLASH register access privileged mode enabled
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
The following values must be written consecutively to unlock FLASH_CR and
FLASH_C2CR, thus enabling programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB
28
27
26
25
w
w
w
w
12
11
10
9
w
w
w
w
24
23
22
KEY[31:16]
w
w
w
8
7
6
KEY[15:0]
w
w
w
24
23
22
OPTKEY[31:16]
w
w
w
8
7
6
OPTKEY[15:0]
w
w
w
RM0453 Rev 1
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
21
20
19
18
w
w
w
w
5
4
3
2
w
w
w
w
RM0453
17
16
w
w
1
0
w
w
17
16
w
w
1
0
w
w
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