ST STM32L4+ Series Reference Manual page 1658

Inter-integrated circuit (I2C) interface
49.4.7 Data transfer
The data transfer is managed through transmit and receive data registers and a shift
register.
Reception
The SDA input fills the shift register. After the 8th SCL pulse (when the complete data byte is
received), the shift register is copied into I2C_RXDR register if it is empty (RXNE=0). If
RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line
is stretched low until I2C_RXDR is read. The stretch is inserted between the 8th and 9th
SCL pulse (before the Acknowledge pulse).
SCL
Shift register
RXNE
I2C_RXDR
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Figure 463. Data reception
xx data1
data0
RM0432 Rev 6
ACK pulse ACK pulse
xx data2
rd data0 rd data1
data1
RM0432
legend:
SCL
stretch
xx
data2
MS19848V1