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Inter-integrated circuit (I2C) interface
SCL high level detected
SCL
SCL released
SCL high level detected
SCLH counter starts
Caution:
In order to be I
below:
1670/2301
Figure 472. Master clock generation
SCL master clock generation
SCLH counter starts
t
SCLH
SYNC2
t
SYNC1
SCL low level detected
SCLL counter starts
SCL driven low
SCL master clock synchronization
SCLH
SCLL
SCL driven low by
another device
SCL low level detected
SCLL counter starts
2
C or SMBus compliant, the master clock must respect the timings given
SCLL
SCL high level detected
SCLH counter starts
SCLH
SCL low level detected
SCLL counter starts
SCL released
RM0432 Rev 6
SCL high level detected
SCLH counter starts
SCLH
SCLL
SCL driven low by
another device
RM0432
MS19858V1
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