Bits 4,5 : Sda/Scl Logic Output Value Monitor Bits Sdam/Sclm; Bits 6,7 : I C System Clock Select Bits Ick0, Ick1; Address Receive In Stop/Wait Mode - Renesas M16C FAMILY series Hardware Manual

M 1 6 C 2 / 8 G o r u p ( M 1 6 C

16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM

The SDAM/SCLM bits can monitor the logic value of the SDA and SCL output signals from the I
interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL
output logic value. The SDAM and SCLM bits are read-only. When write, set them to "0".
16.6.5 Bits 6,7 : I
The ICK1 bit, ICK0 bit, the ICK4 to ICK2 bits in the S4D0 register, and the PCLK0 bit in the PCLKR
register can select the system clock (V
2
The I C bus system clock V
and 1/8 f . f can be selected between f
IIC IIC
2
Table 16.6 I C system clock select bits
I3CK4[S4D0] ICK3[S4D0]
0
0
0
0
0
0
1
( Do not set the combination other than the above)

16.6.6 Address Receive in STOP/WAIT Mode

When WAIT mode is entered after the CM02 bit in the CM0 register is set to "0" (do not stop the peripheral
function clock in wait mode), the I
2
ever, the I C bus interface circuit is not operated in STOP mode or in low power consumption mode,
2
because the I C bus system clock V
R e . v 2 0 . 0 J a . n 3 , 1 2 0 0 7
R E J 0 9 B 0 0 4 7 0 - 2 0 0
2 / , 8 M 1 6 C 2 / 8 ) B
2
C System Clock Select Bits ICK0, ICK1
IIC
can be selected among 1/2 f
IIC
ICK2[S4D0]
0 0
0 0
0 0
0 1
1 0
1 1
0 0
2
C bus interface circuit can receive address data in WAIT mode. How-
is not supplied.
IIC
page 269
f o 3 8 5
2
) of the I C bus interface circuit.
, 1/2.5 f
IIC
and f by the PCLK0 bit setting.
1 2
ICK1[S3D0]
0
0
1
X
X
X
X
2
16. MULTI-MASTER I
, 1/3 f , 1/4 f
IIC IIC IIC
2
ICK0[S3D0] I C system clock
0 V
IIC
1 V
IIC
0 V
IIC
X V
IIC
X V
IIC
X V
IIC
X V
IIC
C bus INTERFACE
2
C bus
, 1/5 f , 1/6 f
IIC IIC
= 1/2 f(X )
IN
= 1/4 f(X )
IN
= 1/8 f(X )
IN
= 1/2.5 f(X )
IN
= 1/3 f(X )
IN
= 1/5 f(X )
IN
= 1/6 f(X )
IN