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M16C/29 Group
14.1.3.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 14.1.3.2.1.
The U2SMR2 register's CSC bit is used to synchronize the internally generated clock (internal SCL2)
and an external clock supplied to the SCL
nization enabled), if a falling edge on the SCL
internal SCL
2
the low-level interval. If the internal SCL
counting stops, and when the SCL
In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL
pin signal. The transfer clock works from a half period before the falling edge of the internal SCL
bit to the rising edge of the 9
The U2SMR2 register's SWC bit allows to select whether the SCL
low-level output at the falling edge of the 9th clock pulse.
If the U2SMR4 register's SCLHI bit is set to "1" (enabled), SCL
impedance state) when a stop condition is detected.
Setting the U2SMR2 register's SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCL
clock) allows the transfer clock to be output from or supplied to the SCL
low-level signal.
If the U2SMR4 register's SWC9 bit is set to "1" (SCL hold low enabled) when the U2SMR3 register's
CKPH bit = 1, the SCL
ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCL
14.1.3.5 SDA Output
The data written to the U2TB register bit 7 to bit 0 (D
The ninth bit (D
The initial value of SDA
register's SMD2 to SMD0 bits = '000
The U2SMR3 register's DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 U2BRG count
source clock cycles to SDA
Setting the U2SMR2 register's SDHI bit = 1 (SDA output disabled) forcibly places the SDA
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UART2
transfer clock. This is because the ABT bit may inadvertently be set to "1" (detected).
14.1.3.6 SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D
bit 7 to bit 0. The 9th bit (D
When the IICM2 bit = 1, the 1st to 7th bits (D
bit 6 to bit 0 and the 8th bit (D
providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the
U2RB register after the rising edge of the corresponding clock pulse of 9th bit.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
goes low, at which time the U2BRG register value is reloaded with and starts counting in
pin goes high, counting restarts.
2
th
bit. To use this function, select an internal clock for the transfer clock.
pin even while sending or receiving data. Clearing the SWC2 bit to "0" (transfer
2
pin is fixed to low-level output at the falling edge of the clock pulse next to the
2
) is ACK or NACK.
8
transmit output can only be set when IICM = 1 (I
2
2
output.
2
) is ACK or NACK.
8
) is stored in the U2RB register bit 8. Even when the IICM2 bit = 1,
0
page 195 of 402
14.1.3 Special Mode 1 (I
pin. In cases when the CSC bit is set to "1" (clock synchro-
2
pin is detected while the internal SCL
2
changes state from low to high while the SCL
2
to D
) is sequentially output beginning with D
7
0
' (serial I/O disabled).
to D
) of received data are stored in the U2RB register
7
0
to D
) of received data are stored in the U2RB register
7
1
2
C bus mode) (UART2)
pin should be fixed to or freed from
2
output is turned off (placed in the high-
2
pin, instead of outputting a
2
pin from low-level output.
2
2
C bus mode) and the U2MR
is high, the
2
pin is low,
2
and SCL
2
2
1st
2
.
7
pin in the
2
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