Synchronous Switching Of Multiple Outputs - NXP Semiconductors freescale KV4 Series Reference Manual

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During deadtime, load inductance

drives voltage with polarity that keeps

inductive current flowing through diodes.

Figure 37-232. Output Pulse Width Measurement Possible with the E-Capture Circuit

37.5.1.7 Synchronous Switching of Multiple Outputs

Before the PWM signals are routed to the output pins, they are processed by a hardware

block that permits all submodule outputs to be switched synchronously. Not only do all

the changes occur synchronously on all submodule outputs, but they occur

IMMEDIATELY after the trigger event occurs eliminating any interrupt latency.

The synchronous output switching is accomplished via a signal called FORCE_OUT.

This signal originates from the local FORCE bit within the submodule, from submodule0,

or from external to the PWM module and, in most cases, is supplied from an external

timer channel configured for output compare. In a typical application, software sets up

the desired states of the output pins in preparation for the next FORCE_OUT event. This

selection lays dormant until the FORCE_OUT signal transitions and then all outputs are

switched simultaneously. The signal switching is performed upstream from the deadtime

generator so that any abrupt changes that might occur do not violate deadtime on the

power stage when in complementary mode.

Freescale Semiconductor, Inc.

Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)

KV4x Reference Manual, Rev. 2, 02/2015

to PWMX input

Actual load voltage

pulse width is measured