Dma Operation; Low-Power Mode Operation - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Table 36-40. Modes of DAC data buffer operation

36.6.2 DMA operation

When DMA is enabled, DMA requests are generated instead of interrupt requests. The

DMA Done signal clears the DMA request.

The status register flags are still set and are cleared automatically when the DMA

36.6.3 Resets

During reset, the DAC is configured in the default mode and is disabled.

The following table shows the wait mode and the stop mode operation of the DAC

Freescale Semiconductor, Inc.

NOTE: A successful 32bit FIFO write will increase the write

NOTE: For 8bit write, address bit[0] determine which byte

In FIFO mode, the DATA BUF will be organized as FIFO.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 36 12-bit Digital-to-Analog Converter (DAC)

pointer by 2. Any write will cause the FIFO over-flow

will be ignored, the cases includes: 1.FIFO is full, the

write will be ignored. 2.FIFO is nearly full

(FIFO_SIZE-1), 32bit write will be ignored.

lane will be written to the FIFO according to little

endian alignment. Only both byte lanes are written

will the write pointer increase. User need to make

sure 8bit access happened in pair and both upper &

lower bytes are written. There is no requirement on

which byte write first. In FIFO mode, there is no

change to read access of DACDATx (from normal

mode), read to DACDATx will return the DATA

addressed by the access address to the data buffer,

and both write pointer and read pointer in FIFO mode

will NOT be changed by read access. FIFO write can

be happened when DAC is not enabled for 1st data

conversion enable. But FIFO mode need to work at

buffer Enabled at DACC1[DACBFEN].