Rxedgif Description; Rxd Edge Detect Sensitivity - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

System level interrupt sources

Interrupt Source

46.7.1 RXEDGIF description

S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Therefore, the

active edge can be detected only when in two wire mode. A RXEDGIF interrupt is

generated only when S2[RXEDGIF] is set. If RXEDGIE is not enabled before

S2[RXEDGIF] is set, an interrupt is not generated.

Edge sensitivity can be software programmed to be either falling or rising. The polarity

of the edge sensitivity is selected using S2[RXINV]. To detect the falling edge,

S2[RXINV] is programmed to 0. To detect the rising edge, S2[RXINV] is programmed

Synchronizing logic is used prior to detect edges. Prior to detecting an edge, the receive

data on RxD input must be at the deasserted logic level. A falling edge is detected when

the RxD input signal is seen as a logic 1 (the deasserted level) during one module clock

cycle, and then a logic 0 (the asserted level) during the next cycle. A rising edge is

detected when the input is seen as a logic 0 during one module clock cycle and then a

logic 1 during the next cycle.

Table 46-79. UART interrupt sources

KV4x Reference Manual, Rev. 2, 02/2015

Local enable

Freescale Semiconductor, Inc.

LBKDDMAS = 0