Arbitration During Undefined Length Bursts - NXP Semiconductors freescale KV4 Series Reference Manual

Functional Description
After the master has control of the slave port it is targeting, the master remains in control
of the slave port until it relinquishes the slave port by running an IDLE cycle or by
targeting a different slave port for its next access.
The master can also lose control of the slave port if another higher-priority master makes
a request to the slave port.
The crossbar terminates all master IDLE transfers, as opposed to allowing the termination
to come from one of the slave buses. Additionally, when no master is requesting access to
a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default
master may be granted access to the slave port.
When a slave bus, other than the flash (if present), is being idled by the crossbar, it
remains parked with the last master to use the slave port. This is done to save the initial
clock of arbitration delay that otherwise would be seen if the same master had to arbitrate
to gain control of the slave port.
If present, the flash slave port parks on the CPU master whenever there is an idle flash
slave port cycle. This is done to save the CPU the initial clock of arbitration delay that
would be seen if the CPU had to gain control of the flash slave port.
20.4.2 Arbitration
The crossbar switch supports two arbitration algorithms:
• Fixed priority
• Round-robin
The selection of the global slave port arbitration is controlled by MCM_PLACR[ARB].
For fixed priority, set MCM_PLACR[ARB] to 0. For round robin, set
MCM_PLACR[ARB] to 1. This arbitration setting applies to all slave ports.

20.4.2.1 Arbitration during undefined length bursts

All lengths of burst accesses lock out arbitration until the last beat of the burst.
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
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