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MPC5606BK Microcontroller

Reference Manual

Devices Supported:

MPC5606BK

MPC5605BK

MPC5606BKRM

Rev. 2

05/2014

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Summary of Contents for NXP Semiconductors MPC5606BK

Page 1 MPC5606BK Microcontroller Reference Manual Devices Supported: MPC5606BK MPC5605BK MPC5606BKRM Rev. 2 05/2014...
Page 2 This page is intentionally left blank.
Page 3 Preface Overview ............................21 Audience ............................21 Guide to this reference manual ......................21 Register description conventions ....................25 References ............................26 How to use the MPC5606BK documents ..................26 1.6.1 The MPC5606BK document set ..................26 1.6.2 Reference manual content ....................27 Using the MPC5606BK ........................28 1.7.1 Hardware design ......................28...
Page 4 Slow internal RC oscillator (SIRC) digital interface ..............111 6.5.1 Introduction ........................111 6.5.2 Functional description ....................112 6.5.3 Register description ......................112 Fast internal RC oscillator (FIRC) digital interface ..............113 6.6.1 Introduction ........................113 6.6.2 Functional description ....................113 6.6.3 Register description ......................114 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 5 Register descriptions ....................150 Functional description ........................163 8.4.1 Mode transition request ....................163 8.4.2 Modes details ........................164 8.4.3 Mode transition process ....................167 8.4.4 Protection of mode configuration registers ..............175 8.4.5 Mode transition interrupts ....................175 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 6 11.1 Voltage regulators ..........................207 11.1.1 High power regulator (HPREG) ...................207 11.1.2 Low power regulator (LPREG) ..................207 11.1.3 Ultra low power regulator (ULPREG) .................208 11.1.4 LVDs and POR ......................208 11.1.5 VREG digital interface ....................208 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 7 RTC Control Register (RTCC) ..................231 13.5.3 RTC Status Register (RTCS) ..................233 13.5.4 RTC Counter Register (RTCCNT) ................234 13.6 RTC functional description ......................234 13.7 API functional description ......................235 Chapter 14 CAN Sampler 14.1 Introduction ...........................237 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8 DMA arbitration mode considerations .................286 16.5.5 DMA transfer ........................287 16.5.6 TCD status ........................290 16.5.7 Channel linking ......................291 16.5.8 Dynamic programming ....................292 Chapter 17 eDMA Channel Multiplexer (DMA_MUX) 17.1 Introduction ...........................295 17.2 Features ............................295 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 9 Lowering priority within an ISR ..................338 18.7.9 Negating an interrupt request outside of its ISR ............338 18.7.10 Examining LIFO contents ....................339 Chapter 19 Crossbar Switch (XBAR) 19.1 Introduction ...........................341 19.2 Block diagram ..........................341 19.3 Overview ............................342 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 Memory map ........................378 21.5.2 Register description ......................379 21.6 Functional description ........................390 21.6.1 Access evaluation macro ....................390 21.6.2 Putting it all together and AHB error terminations ............391 21.7 Initialization information .......................392 21.8 Application information ........................392 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 11 Loop Back mode ......................426 23.6.2 Self Test mode ......................427 23.7 Memory map and registers description ..................427 23.7.1 Memory map ........................427 23.8 Functional description ........................453 23.8.1 UART mode ........................453 23.8.2 LIN mode ........................455 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 12 LIN timeout control status register (LINTCSR) ............502 24.10.8 LIN output compare register (LINOCR) ..............503 24.10.9 LIN timeout control register (LINTOCR) ..............504 24.10.10 LIN fractional baud rate register (LINFBRR) ..............505 24.10.11 LIN integer baud rate register (LINIBRR) ..............505 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 13 25.2 Introduction ...........................547 25.2.1 Overview ........................548 25.2.2 FlexCAN module features ....................549 25.2.3 Modes of operation .......................549 25.3 External signal description ......................550 25.3.1 Overview ........................550 25.3.2 Signal descriptions ......................551 25.4 Memory map/register definition ....................551 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 14 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ............614 26.5.8 DSPI POP RX FIFO Register (DSPIx_POPR) ............616 26.5.9 DSPI Transmit FIFO Registers 0–3 (DSPIx_TXFRn) ..........617 26.6 Functional description ........................618 26.6.1 Modes of operation .......................619 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 Memory map and register description ................705 27.5.5 Functional description ....................709 27.5.6 Initialization and application information ..............710 Chapter 28 Analog-to-Digital Converter (ADC) 28.1 Overview ............................715 28.1.1 Device-specific features ....................715 28.1.2 Device-specific implementation ...................716 28.2 Introduction ...........................717 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 30.1 Introduction ...........................789 30.2 Main features ..........................790 30.3 Block diagram ..........................790 30.4 Functional description ........................791 30.4.1 Module structure ......................791 30.4.2 Flash memory module sectorization ................792 30.4.3 TestFlash block ......................793 30.4.4 Shadow sector .......................795 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 31.6 Initialization and application information ..................891 Chapter 32 Register Protection 32.1 Introduction ...........................895 32.2 Features ............................895 32.3 Modes of operation ........................896 32.4 External signal description ......................896 32.5 Memory map and register description ...................896 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 18 IEEE 1149.1-2001 defined test modes .................946 35.6 External signal description ......................947 35.7 Memory map and register description ...................947 35.7.1 Instruction register ......................947 35.7.2 Bypass register ......................948 35.7.3 Device identification register ..................948 35.7.4 Boundary scan register ....................949 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 19 OnCE controller block diagram ...............953 35.9.2 e200z0 OnCE controller functional description ............954 35.9.3 e200z0 OnCE controller register description ...............954 35.10 Initialization/application information ....................956 Appendix A Revision History Changes between revisions 1 and 2 ....................957 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 20 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21 This manual is intended for system software and hardware developers and applications programmers who want to develop products with the MPC5606BK device. It is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hardware, and basic details of the Power Architecture.
Page 22 CAN Sampler Details on how to configure the CAN sampler, which is used to capture the identifier frame of a CAN message when the microcontroller is in low power mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 23 Some of these modules support DMA requests to fill / LIN Controller (LINFlex) empty buffer queues to minimize CPU overhead. LIN Controller (LINFlexD) FlexCAN Deserial Serial Peripheral Interface (DSPI) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 24 (with ECC), block sizes and the flash memory port configuration, including wait states, line buffer configuration, and pre-fetch control. Static RAM (SRAM) Details the structure of the SRAM (with ECC). There are no user configurable registers associated with the SRAM. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 25 W FIELD1 FIELD2 Write-only fields “Write 1 to clear” field (field will always read 0) Figure 1-1. Register figure conventions The numbering of register bits and fields on MPC5606BK is as follows: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 26 Power Architecture Book E V1.0 (http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf) How to use the MPC5606BK documents This section: • Describes how the MPC5606BK documents provide information on the microcontroller • Makes recommendations on how to use the documents in a system design 1.6.1 The MPC5606BK document set The MPC5606BK document set comprises: •...
Page 27 Implementation of the boot options if internal flash memory is not used Clock Description Clocking architecture of the device (which Description of operation of different clock clock is available for the system and each sources peripheral) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 28 Using the MPC5606BK There are many different approaches to designing a system using the MPC5606BK so the guidance in this section is provided as an example of how the documents can be applied in this task.
Page 29 Mode Entry Module (MC_ME) — controls the operating mode the MCU is in and configures the peripherals, clocks, and power supplies for each of the modes • Power Control Unit (MC_PCU) — determines which power domains are active MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 30 Individual register settings can be protected from unintended writes using the features of the Register Protection module. The protected registers are shown in Chapter 32, Register Protection. Other integration functionality is provided by the System Status and Configuration Module (SSCM). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 31 • Seat control The MPC5606BK family expands the range of the MPC560xB/C microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the MPC5606BK automotive controller family complies with the Power Architecture embedded category, and only implements the VLE (variable-length encoding) APU, providing improved code density.
Page 32 Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare. Maximum I/O count based on multiplexing with peripherals. Device block diagram Figure 2-1 shows a top-level block diagram of the MPC5606BK. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 33 System Timer Module INTC Interrupt Controller Software Watchdog Timer JTAG JTAG controller WKPU Wakeup Unit Figure 2-1. MPC5606BK block diagram Table 2-2 summarizes the functions of the blocks present on the MPC5606BK. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 34 Chapter 2 Introduction Table 2-2. MPC5606BK series block summary Block Function Analog-to-digital converter (ADC) Converts analog voltages to digital values Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device...
Page 35 Multi-cycle divide word (divw) and load multiple word (lmw) store multiple word (smw) multiple class instructions, can be interrupted to prevent increases in interrupt latency 2.4.2 Crossbar switch (XBAR) The following summarizes the MPC5606BK’s implementation of the crossbar switch: • Three master ports: — CPU instruction bus —...
Page 36 Support for two 32-bit virtual ports via the DSPI serialization 2.4.5 Flash memory The on-chip flash memory on the MPC5606BK features the following: • As much as 1.0 MB burst flash memory — 4  128-bit page buffers with programmable prefetch control —...
Page 37 Flash_Base + 0x000C_0000 — 128 KB Flash_Base + 0x000E_0000 — 128 KB Array_C Flash_Base + 0x0010_0000 — — Flash_Base + 0x0012_0000 — — Flash_Base + 0x0014_0000 — — Flash_Base + 0x0016_0000 — — MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 38 16 KB 16 KB 2.4.6 SRAM The on-chip SRAM on the MPC5606BK features the following: • As much as 80 KB general purpose SRAM • Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block •...
Page 39 Chapter 2 Introduction 2.4.9 Enhanced Modular Input Output System (eMIOS) The MPC5606BK implements a scaled-down version of the eMIOS module: • As many as 64 timed I/O channels with 16-bit counter resolution • Buffered updates • Support for shifted PWM outputs to minimize occurrence of concurrent edges •...
Page 40 32-bit serialization of data enabling virtual GPIO ports on 2 DSPI modules 2.4.11 Controller Area Network module (FlexCAN) The enhanced FlexCAN module features the following: • As many as six FlexCAN modules supported MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 41 — Supports capturing of first message identifier while in STOP or STANDBY modes 2.4.12 System clocks and clock generation The following list summarizes the system clock and clock generation on the MPC5606BK: • System clock can be derived from the following sources —...
Page 42 — 1 sec resolution for > 1 hour period — 1 ms resolution for 2 second period • Selectable clock sources — 128 kHz slow internal RC oscillator — Divided 16 MHz fast internal RC oscillator MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 43 — External 32 KHz crystal • Supports continued operation through all resets except POR (power-on reset) 2.4.14 System watchdog timer The watchdog on the MPC5606BK features the following: • Activation by software or out of reset • 32-bit modulus counter •...
Page 44 — Internal conversion triggering from periodic interrupt timer (PIT) or timed I/O module (eMIOS) through cross triggering unit (CTU) — Internal conversion triggering from periodic interrupt timer (PIT) — One input pin configurable as external conversion trigger source MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 45 Separate dedicated DMA request for injection mode 2.4.18 Enhanced Direct Memory Access controller (eDMA) The following summarizes the MPC5606BK’s implementation of the eDMA controller: • 16 channels to support independent 8-, 16-, or 32-bit single value or block transfers •...
Page 46 • Synchronization with ADC to avoid collision 2.4.20 Serial communication interface module (LINFlex) The LINFlex on the MPC5606BK features the following: • As many as eight LINFlex modules supported • Supports LIN master mode, LIN slave mode and UART mode •...
Page 47 All JTAG pins reusable in application as standard IOs Developer support The MPC5606BK MCU tools and third-party developers are similar to those used for the Freescale MPC5500 product family, offering a widespread, established network of tool and software vendors. The following development support will be available: •...
Page 48 Chapter 2 Introduction This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 49 Chapter 3 Memory Map Table 3-1 shows the memory map for the MPC5606BK. All addresses on the device, including those that are reserved, are identified in the table. The addresses represent the physical addresses assigned to each IP block. Table 3-1. MPC5606BK memory map...
Page 50 Chapter 3 Memory Map Table 3-1. MPC5606BK memory map (continued) Start address End address Size (KB) Region name 0x4001_4000 0xBFFF_FFFF 2097072 Reserved Off-platform peripherals 0xC000_0000 0xC3F8_7FFF 65056 Reserved 0xC3F8_8000 0xC3F8_BFFF Code flash memory 0 configuration 0xC3F8_C000 0xC3F8_FFFF Data flash memory 0 configuration...
Page 51 Chapter 3 Memory Map Table 3-1. MPC5606BK memory map (continued) Start address End address Size (KB) Region name 0xFFE6_4000 0xFFE6_7FFF 0xFFE6_8000 0xFFE6_FFFF Reserved 0xFFE7_0000 0xFFE7_3FFF CAN sampler 0xFFE7_4000 0xFFE7_FFFF Reserved 0xFFE8_0000 0xFFEF_FFFF Mirrored range 0x3F80000—0xC3FFFFFF 0xFFF0_0000 0xFFF0_FFFF Reserved 0xFFF1_0000 0xFFF1_3FFF...
Page 52 Chapter 3 Memory Map This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 53 PB[13] VSS_HV PD[13] Top view VDD_HV PB[12] VSS_HV VDD_HV_ADC1 RESET VSS_HV_ADC1 VSS_LV PD[11] VDD_LV PD[10] VDD_BV PD[9] PC[11] PB[7] PC[10] PB[6] PB[0] PB[5] PB[1] VDD_HV_ADC0 PC[6] VSS_HV_ADC0 Figure 4-1. 100-pin LQFP pinout MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 54 PD[14] VDD_BV PB[13] PG[9] PD[13] PG[8] PB[12] PC[11] VDD_HV_ADC1 PC[10] VSS_HV_ADC1 PG[7] PD[11] PG[6] PD[10] PB[0] PD[9] PB[1] PB[7] PF[9] PB[6] PF[8] PB[5] PF[12] VDD_HV_ADC0 PC[6] VSS_HV_ADC0 Figure 4-2. 144-pin LQFP pinout MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 55 Each entry of Table 4-1 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 56 Tristate E0UC[6] eMIOS_0 — — — CS1_1 DSPI_1 — EIRQ[1] SIUL — LIN4RX LINFlex_4 PA[7] PCR[7] GPIO[7] SIUL Tristate E0UC[7] eMIOS_0 LIN3TX LINFlex_3 — — — — EIRQ[2] SIUL — ADC1_S[1] ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 57 — — PA[14] PCR[14] GPIO[14] SIUL Tristate SCK_0 DSPI_0 CS0_0 DSPI_0 E0UC[0] eMIOS_0 — EIRQ[4] SIUL PA[15] PCR[15] GPIO[15] SIUL Tristate CS0_0 DSPI_0 SCK_0 DSPI_0 E0UC[1] eMIOS_0 — WKUP[10] WKUP Port B MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 58 ADC0_P[1] ADC_0 — ADC1_P[1] ADC_1 — GPIO[21] SIUL PB[6] PCR[22] — — — Tristate — — — — — — — — — — ADC0_P[2] ADC_0 — ADC1_P[2] ADC_1 — GPIO[22] SIUL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 59 ADC0_S[3] ADC_0 PB[12] PCR[28] GPIO[28] SIUL Tristate E0UC[4] eMIOS_0 — — — CS1_0 DSPI_0 — ADC0_X[0] ADC_0 PB[13] PCR[29] GPIO[29] SIUL Tristate E0UC[5] eMIOS_0 — — — CS2_0 DSPI_0 — ADC0_X[1] ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 60 SIUL Tristate E1UC[31] eMIOS_1 — — — DEBUG[2] SSCM — EIRQ[18] SIUL — SIN_1 DSPI_1 — CAN3RX FlexCAN_3 PC[5] PCR[37] GPIO[37] SIUL Tristate SOUT_1 DSPI_1 CAN3TX FlexCAN_3 DEBUG[3] SSCM — EIRQ[7] SIUL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 61 EIRQ[19] SIUL — SIN_2 DSPI_2 PC[13] PCR[45] GPIO[45] SIUL Tristate E0UC[13] eMIOS_0 SOUT_2 DSPI_2 — — — PC[14] PCR[46] GPIO[46] SIUL Tristate E0UC[14] eMIOS_0 SCK_2 DSPI_2 — — — — EIRQ[8] SIUL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 62 — — — — — — — ADC0_P[8] ADC_0 — ADC1_P[8] ADC_1 PD[5] PCR[53] GPIO[53] SIUL Tristate — — — — — — — — — — ADC0_P[9] ADC_0 — ADC1_P[9] ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 63 PD[12] PCR[60] GPIO[60] SIUL Tristate — — CS5_0 DSPI_0 E0UC[24] eMIOS_0 — — — — ADC0_S[4] ADC_0 PD[13] PCR[61] GPIO[61] SIUL Tristate CS0_1 DSPI_1 E0UC[25] eMIOS_0 — — — — ADC0_S[5] ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 64 DSPI_1 — — — — EIRQ[9] SIUL PE[5] PCR[69] GPIO[69] SIUL Tristate E0UC[21] eMIOS_0 CS0_1 DSPI_1 MA[2] ADC_0 PE[6] PCR[70] GPIO[70] SIUL Tristate E0UC[22] eMIOS_0 CS3_0 DSPI_0 MA[1] ADC_0 — EIRQ[22] SIUL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 65 — ADC1_S[7] ADC_1 PE[13] PCR[77] GPIO[77] SIUL Tristate — SOUT_2 DSPI_2 E1UC[20] eMIOS_1 — — — PE[14] PCR[78] GPIO[78] SIUL Tristate — SCK_2 DSPI_2 E1UC[21] eMIOS_1 — — — — EIRQ[12] SIUL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 66 PCR[86] GPIO[86] SIUL Tristate — E0UC[23] eMIOS_0 CS1_1 DSPI_1 — — — — ADC0_S[14] ADC_0 PF[7] PCR[87] GPIO[87] SIUL Tristate — — — — CS2_1 DSPI_1 — — — — ADC0_S[15] ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 67 — CAN4TX FlexCAN_4 E1UC[27] eMIOS_1 CAN1TX FlexCAN_1 PF[15] PCR[95] GPIO[95] SIUL Tristate — E1UC[4] eMIOS_1 — — — — — — — EIRQ[13] SIUL — CAN1RX FlexCAN_1 — CAN4RX FlexCAN_4 Port G MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 68 GPIO[103] SIUL Tristate — E1UC[16] eMIOS_1 E1UC[30] eMIOS_1 — — — — WKUP[20] WKUP — LIN6RX LINFlex_6 PG[8] PCR[104] GPIO[104] SIUL Tristate — E1UC[17] eMIOS_1 LIN7TX LINFlex_7 CS0_2 DSPI_2 — EIRQ[15] SIUL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 69 Port H PH[0] PCR[112] GPIO[112] SIUL Tristate — E1UC[2] eMIOS_1 — — — — — — — SIN_1 DSPI_1 PH[1] PCR[113] GPIO[113] SIUL Tristate — E1UC[3] eMIOS_1 SOUT_1 DSPI_1 — — — MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 70 JTAGC pull-up — — — PH[11] PCR[123] GPIO[123] SIUL Tristate — — SOUT_3 DSPI_3 CS0_4 DSPI_4 E1UC[5] eMIOS_1 PH[12] PCR[124] GPIO[124] SIUL Tristate — — SCK_3 DSPI_3 CS1_4 DSPI_4 E1UC[25] eMIOS_1 — MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 71 DSPI_4 — — — PI[5] PCR[133] GPIO[133] SIUL Tristate — — E1UC[29] eMIOS_1 SCK_4 DSPI_4 — — — PI[6] PCR[134] GPIO[134] SIUL Tristate — — E1UC[30] eMIOS_1 CS0_4 DSPI_4 — — — MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 72 — — — — — — — — — ADC0_S[22] ADC_0 — SIN_4 DSPI_4 PI[15] PCR[143] GPIO[143] SIUL Tristate — — CS0_4 DSPI_4 — — — — — — — ADC0_S[23] ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 73 4-2. The RESET configuration applies during and after reset. All WKUP pins also support external interrupt capability. See the WKPU chapter of the MPC5606BK Microcontroller Reference Manual for further details. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
Page 74 AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset value of PCR.OBE = 1. Not available in 100LQFP package. Table 4-2. Pad types Type Description Fast Input only with analog feature Input/output with analog feature Medium Slow MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 75 The SSCM preforms a lot of the automated boot activity including reading the latched value of the FAB (PA[9]) pin to determine whether to boot from flash memory or serial boot mode. This is illustrated in Figure 5-1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 76 — A BOOT_ID field that must be correctly set to 0x5A in order to “validate” the boot sector • 32-bit reset vector (this is the start address of the user code) The location and structure of the boot sectors in flash memory are shown in Figure 5-2. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 77 BAM address and the core starts to execute the code to enter static mode as follows: • The core executes the “wait” instruction, which halts the core. The sequence is illustrated in Figure 5-3. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 78 • JTAG debug interface • Serial boot mode (which could otherwise be used to download and execute code to query or modify the flash memory) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 79 Each 32-bit register is split into an upper and lower 16-bit field. The upper 16 bits (the SC field) are used to control serial boot mode censorship. The lower 16 bits (the CW field) are used to control flash memory boot censorship. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 80 — to modify the CW field in both NVSCC0,1 registers so they match but do not equal 0x55AA. This will allow you to enter the private password in both serial and flash boot modes. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 81 NVSCC0,1 registers as well as detailing the correct way to enter the serial password. In the password examples, assume the 64-bit password has been programmed into the shadow flash memory in the order {NVPWD0, NWPWD1} and has a value of 0x01234567_89ABCDEF. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 82 Censored with True Enter password as Note: CW != 0x55AA private password {NVPWD1, NVPWD0} SC = 0x55AA over JTAG example – 0x89ABCDEF_01234567 False Uncensored Figure 5-4. Censorship control in flash memory boot mode MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 83 Places the microcontroller into static mode if flash memory boot mode is selected and a valid BOOT_ID is not located in one of the boot sectors by the SSCM 5.2.1 BAM software flow Figure 5-6 illustrates the BAM logic flow. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 84 In static mode a wait instruction is executed to halt the core. For the FlexCAN and LINFlex serial boot modes, the respective area of BAM code is executed to download the code to SRAM. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 85 1. Since the device supports only VLE code and not Book E code, this flag is used only for backward compatibility. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 86 BAM code. In this case the SSCM is used to obtain the private password from the flash memory of the censored device. When the SSCM reads the private password it inverts the order of {NVPWD0, NWPWD1} so the password entered over the serial download needs to be {NVPWD1, NVPWD0}. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 87 2. If the private password is used, the BAM code does a direct comparison between the serial password and the private password in flash memory, {NVPWD0, NVPWD1}. 3. If the password does not match, the BAM code immediately terminates the download and pushes the microcontroller into static mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 88 7. Finally, the BAM code reads SEC. If SEC = 0, execution is transferred to the code in the SRAM. If SEC = 1, the BAM code forces the microcontroller into static mode. Figure 5-8 shows this in more detail. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 89 With LINFlex, any receive error will result in static mode. With FlexCAN, the host will retransmit data if there has been no acknowledgment from the microcontroller. However, there could be a situation where the receiver configuration has an error, which would result in static mode entry. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 90 Since the SRAM is protected by 32-bit wide Error Correction Code (ECC), the BAM code always writes bytes into SRAM grouped into 32-bit words. If the last byte received does not fall onto a 32-bit boundary, the BAM code fills any additional bytes with 0x0. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 91 1 stop bit. Byte field Start Stop Figure 5-10. LINFlex bit timing in UART mode 5.2.2.2 Protocol Table 5-8 summarizes the protocol and BAM action during this boot mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 92 It uses the standard 11-bit identifier format detailed in FlexCAN 2.0A specification. FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta before the end, as shown in Figure 5-11. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 93 SRAM starting from the “Load address”. binary data binary data “Load address” increments until the number of data received and stored matches the size as specified in the previous step. None None Branch to downloaded code MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 94 — Microcontroller Mode and Security Status (including censorship and serial boot information) — Search Code Flash for bootable sector — Determine boot vector • Device identification information (MCU ID registers) • Debug Status Port enable and selection • Bus and peripheral abort enable/disable MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 95 PUB SEC BMODE Reset Figure 5-13. System Status Register (SSCM_STATUS) Table 5-11. SSCM_STATUS allowed register accesses Access type 8-bit 16-bit 32-bit Read Allowed Allowed Allowed Write Not allowed Not allowed Not allowed MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 96 The System Memory Configuration register is a read-only register that reflects the memory configuration of the system. Offset: 0x02 Access: Read PRSZ PVLB DTSZ DVLD Reset Figure 5-14. System Memory Configuration Register (SSCM_MEMCONFIG) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 97 5.3.4.3 Error Configuration (SSCM_ERROR) The Error Configuration register is a read-write register that controls the error handling of the system. Offset: 0x06 Access: Read/write PAE RAE Reset Figure 5-15. Error Configuration (SSCM_ERROR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 98 011 Mode 3 selected 100 Mode 4 selected 101 Mode 5 selected 110 Mode 6 selected 111 Mode 7 selected Table 5-18 describes the functionality of the Debug Status Port in each mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 99 All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). 5.3.4.5 Password comparison registers These registers provide a means for the BAM code to unsecure the device via the SSCM if the password has been provided via serial download. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 100 Table 5-21. SSCM_PWCMPH/L allowed register accesses Access type 8-bit 16-bit 32-bit Read Allowed Allowed Allowed Write Not allowed Not allowed Allowed All 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xC). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 101 SSCM_PWCMPH register, then the lower word to the SSCM_PWCMPL register. The SSCM compares the 64-bit password entered into the SSCM_PWCMPH / SSCM_PWCMPL registers with the NVPWM[1,0] private password stored in the shadow flash. If the passwords match then the SSCM temporarily uncensors the microcontroller. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 102 Chapter 5 Microcontroller Boot This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 103 ——— Clocks and power ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 104 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 105 Chapter 6 Clock Description Chapter 6 Clock Description This chapter describes the clock architectural implementation for MPC5606BK. Clock architecture System clocks are generated from three sources: • Fast external crystal oscillator 4–16 MHz (FXOSC) • Fast internal RC oscillator 16 MHz (FIRC) •...
Page 106 Figure 6-1. MPC5606BK system clock generation Clock gating The MPC5606BK provides the user with the possibility of gating the clock to the peripherals. Table 6-1 describes for each peripheral the associated gating register address. See the ME_PCTLn section in this reference manual.
Page 107 Chapter 6 Clock Description Table 6-1. MPC5606BK — Peripheral clock sources (continued) Register gating address offset Peripheral Peripheral set (base = 0xC3FD_C0C0) FlexCAN_n 16 + n (n = 0..5) ADC_0 ADC_1 LINFlex_n 48 + n (n = 0..7) CANS —...
Page 108 This division factor is specified by FXOSC_CTL[OSCDIV] field. 6.3.3 Register description Address: 0xC3FE_0000 Access: Special read/write EOCV RESET: OSCDIV RESET: Figure 6-2. Fast External Crystal Oscillator Control Register (FXOSC_CTL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 109 Output clock division factors ranging from 1 to 32 6.4.3 Functional description The SXOSC circuit includes an internal oscillator driver and an external crystal circuitry. It can be used as a reference clock to specific modules depending on system needs. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 110 This division factor is specified by SXOSC_CTL[OSCDIV] field. 6.4.4 Register description Address: 0xC3FE_0040 Access: Special read/write EOCV RESET: OSCDIV RESET: Figure 6-3. Slow External Crystal Oscillator Control Register (SXOSC_CTL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 111 OFF in standby by setting the OSCON bit. Slow internal RC oscillator (SIRC) digital interface 6.5.1 Introduction The SIRC digital interface controls the 128 kHz slow internal RC oscillator (SIRC). It holds control and status registers accessible for application. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 112 Please refer to the device datasheet for average frequency variation of the trimming step. 6.5.3 Register description Address: 0xC3FE_0080 Access: Read/write SIRCTRIM RESET: SIRCDIV RESET: Figure 6-4. Low Power RC Control Register (SIRC_CTL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 113 In this oscillator, two's complement trimming method is implemented. So the trimming code increases from –32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces. Please refer to the device datasheet for average frequency variation of the trimming step. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 114 This field specifies the FIRC oscillator output clock division factor. The output clock is divided by the factor FIRCDIV+1. FIRCON_STDB FIRC control in STANDBY mode. 0 FIRC is switched off in STANDBY mode. 1 FIRC is in STANDBY mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 115 Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor and output clock divider ratio are all software configurable. MPC5606BK has one FMPLL that can generate the system clock and takes advantage of the FM mode. NOTE The user must take care not to program the device with a frequency higher than allowed (no hardware check).
Page 116 The FMPLL operation is controlled by two registers. Those registers can be accessed and written in supervisor mode only. 6.7.5.1 Control Register (CR) Offset: 0x0 Access: Supervisor read/write NDIV Reset Reset Figure 6-7. Control Register (CR) 1. FMPLL_x are mapped through the ME_CGM register slot MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 117 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 118 Table 6-12. Loop divide ratios NDIV[6:0] Loop divide ratios 0000000–0011111 — 0100000 Divide by 32 0100001 Divide by 33 0100010 Divide by 34 1011111 Divide by 95 1100000 Divide by 96 1100001–1111111 — MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 119 The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following formula: ------------------- - modperiod  where: : represents the frequency of the feedback divider : represents the modulation frequency MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 120 IDF, NDIV, and ODF are set in the CR and can be derived from Table 6-10, Table 6-11, Table 6-12. Table 6-14. FMPLL lookup table CR field values Crystal frequency FMPLL output VCO frequency (MHz) (MHz) frequency (MHz) NDIV MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 121 FMPLL digital interface when the modulation is enabled (FM_EN goes high) if the FMPLL is locked (S_LOCK = 1), or when the modulation has been enabled (FM_EN = 1) and FMPLL enters lock state (S_LOCK goes high). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 122 Once the PLL has been locked, only the output divider can be changed. • Use PLL progressive clock switching to ramp system clock (/8, /4, /2, /1) automatically for the case when PLL is enabled and selected as system clock. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 123 External oscillator clock monitoring with respect to FIRC_clk/n clock • FMPLL clock frequency monitoring for a high and low frequency range with FIRC as reference clock • Event generation for various failures detected inside monitoring unit MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 124 • FXOSC_clk: clock coming from the fast external crystal oscillator • SXOSC_clk: clock coming from the slow external crystal oscillator • SIRC_clk: clock coming from the slow (low frequency) internal RC oscillator MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 125 A failure event FLL is signaled to the MC_RGM, which in turn can generate an interrupt or safe mode request or functional reset, depending on the programming model. NOTE Functional FMPLL monitoring can only be guaranteed when the FMPLL frequency is greater than (FIRC / 4) + 0.5 MHz. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 126 High Frequency Reference Register FMPLL (CMU_HFREFR) 0x08 0x00000FFF on page 128 Low Frequency Reference Register FMPLL (CMU_LFREFR) 0x0C 0x00000000 on page 129 Interrupt Status Register (CMU_ISR) 0x10 0x00000000 on page 129 1. x = FIRC,SIRC or SXOSC MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 127 00 Clock divided by 1 (No division) 01 Clock divided by 2 10 Clock divided by 4 11 Clock divided by 8 CME_A FMPLL_0 clock monitor enable. 0 FMPLL_0 monitor disabled. 1 FMPLL_0 monitor enabled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 128 Field Description HFREF High Frequency reference value. This field determines the high reference value for the FMPLL clock. The reference value is given by: (HFREF  16) × (f  4). FIRC MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 129 This field determines the low reference value for the FMPLL. The reference value is given by: (LFREF  16) × (f  4). FIRC 6.8.5.5 Interrupt Status Register (CMU_ISR) Offset: 0x10 Access: Read/write Reset Reset Figure 6-16. Interrupt status register (CMU_ISR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 130 This field shows the measurement duration in numbers of clock cycles of the selected clock source. This value is loaded in the frequency meter downcounter. When CMU_CSR[SFM] = 1, the downcounter starts counting. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 131 MC_CGM memory space. The MC_CGM also selects and generates an output clock. Figure 7-1 shows the MC_CGM block diagram. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 132 Figure 7-1. MC_CGM block diagram Features The MC_CGM includes the following features: • Generates system and peripheral clocks • Selects and enables/disables the system clock supply from system clock sources according to MC_ME control MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 133 Aux Clock 0 Select word read read/write read/write on page 141 Control NOTE Any access to unused registers as well as write accesses to read-only registers will: • Not change register content MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 134 _0080 … SIRC registers 0xC3FE _009C 0xC3FE _00A0 … FMPLL registers 0xC3FE _00BC 0xC3FE _00C0 … reserved 0xC3FE _00DC 0xC3FE _00E0 … reserved 0xC3FE _00FC 0xC3FE _0100 … CMU registers 0xC3FE _011C MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 135 0xC3FE _019C 0xC3FE _01A0 … reserved 0xC3FE _01BC 0xC3FE _01C0 … reserved 0xC3FE _01DC 0xC3FE _01E0 … reserved 0xC3FE _01FC 0xC3FE _0200 … reserved 0xC3FE _021C 0xC3FE _0220 … reserved 0xC3FE _023C MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 136 0xC3FE _02BC 0xC3FE _02C0 … reserved 0xC3FE _02DC 0xC3FE _02E0 … reserved 0xC3FE _02FC 0xC3FE _0300 … reserved 0xC3FE _031C 0xC3FE _0320 … reserved 0xC3FE _033C 0xC3FE _0340 … reserved 0xC3FE _035C MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 137 All registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the CGM_OC_EN register may be accessed as a word at address 0xC3FE_0370, as a half-word at address 0xC3FE_0372, or as a byte at address 0xC3FE_0373. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 138 Reset Reset Figure 7-3. Output Clock Division Select Register (CGM_OCDS_SC) This register is used to select the current output clock source and its division factor before being delivered at the output clock. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 139 Divided by system clock divider 2: peripheral set 3 clock Figure 7-7 for details. Address 0xC3FE_0378 Access: User read, Supervisor read, Test read SELSTAT Reset Reset Figure 7-4. System Clock Select Status Register (CGM_SC_SS) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 140 If the DE0 is set to 0 (Divider 0 is disabled), any write access to the DIV0 field is ignored and the peripheral set 1 clock remains disabled. Divider 1 Enable 0 Disable system clock divider 1 1 Enable system clock divider 1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 141 0000 FXOSC 0001 FIRC 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 142 MC_RGM safe clock request MC_ME clock select CGM_SC_DC1 Register CGM_SC_SS Register peripheral set 2 clock clock divider CGM_SC_DC2 Register peripheral set 3 clock clock divider Figure 7-7. MC_CGM System Clock Generation Overview MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 143 4-16 MHz ext. xtal osc. 16 MHz int. RC osc. freq. mod. PLL system clock CGM_OC_EN Register RTC clock PA[0] CGM_OCDS_SC.SELDIV CGM_OCDS_SC.SELCTL Register Register Figure 7-8. MC_CGM Output Clock Multiplexer and PA[0] Generation MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 144 The non-divided signal is not guaranteed to be 50% duty cycle by the MC_CGM. • the MC_CGM also has an output clock enable register (see Section 7.5.1.1, Output Clock Enable Register (CGM_OC_EN)), which contains the output clock enable/disable control bit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 145 • Control of the available modes by the ME_ME register • Definition of various device mode configurations by the ME_<mode>_MC registers • Control of the actual device mode by the ME_MCTL register MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 146 & power configurations of the system with interrupt event via software or respect to each other. from HALT, hardware failure, interrupt or wakeup other RUN0…3 event from STOP modes, HALT, STOP via software MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 147 155 _C010 0xC3FD ME_IMTS Invalid Mode Transition word read read/write read/write on page 156 _C014 Status 0xC3FD ME_DMTS Debug Mode Transition word read read read on page 157 _C018 Status MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 148 Any access to unused registers as well as write accesses to read-only registers will: • Not change register content • Cause a transfer error Table 8-3. MC_ME Memory Map S_SYSCLK 0xC3FD ME_MCTL TARGET_MODE _C004 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 149 ME_ME _C008 0xC3FD ME_IS _C00C w1c w1c w1c w1c 0xC3FD ME_IM _C010 0xC3FD ME_IMTS _C014 w1c w1c w1c w1c w1c 0xC3FD ME_DMTS _C018 0xC3FD reserved _C01C 0xC3FD ME_RESET_ _C020 DFLAON CFLAON SYSCLK MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 150 Unless otherwise noted, all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. The bytes are ordered according to big endian. For example, the ME_RUN_PC0 register may be accessed MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 151 S_MVR Main voltage regulator status 0 Main voltage regulator is not ready 1 Main voltage regulator is ready for use MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 152 This register is used to trigger software-controlled mode changes. Depending on the modes as enabled by ME_ME register bits, configurations corresponding to unavailable modes are reserved and access to ME_<mode>_MC registers must respect this for successful mode requests. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 153 Figure 8-4. Mode Enable Register (ME_ME) This register allows a way to disable the device modes that are not required for a given device. RESET, SAFE, DRUN, and RUN0 modes are always enabled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 154 0 RESET mode is disabled 1 RESET mode is enabled 8.3.1.4 Interrupt Status Register (ME_IS) Address 0xC3FD_C00C Access: User read, Supervisor read/write, Test read/write Reset Reset Figure 8-5. Interrupt Status Register (ME_IS) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 155 Invalid mode configuration interrupt mask 0 Invalid mode interrupt is masked 1 Invalid mode interrupt is enabled M_IMODE Invalid mode interrupt mask 0 Invalid mode interrupt is masked 1 Invalid mode interrupt is enabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 156 ME_ME register. It is cleared by writing a 1 to this bit. 0 Target mode requested is not a disabled mode 1 Target mode requested is a disabled mode MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 157 ME_GS.S_MTRANS may be taking longer than expected. NOTE The ME_DMTS register does not indicate whether a mode transition is ongoing. Therefore, some ME_DMTS bits may still be asserted after the mode transition has completed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 158 It is cleared when the DFLASH has completed its state change. 0 No state change is taking place 1 A state change is taking place MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 159 Figure 8-10. TEST Mode Configuration Register (ME_TEST_MC) This register configures system behavior during TEST mode. Please see Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 160 This register configures system behavior during DRUN mode. Please see Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. NOTE The values of CFLAON, and DFLAON are retained through STANDBY mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 161 8.3.1.14 STOP Mode Configuration Register (ME_STOP_MC) This register configures system behavior during STOP mode. Please see Table 8-11 for details. NOTE Byte and half-word write accesses are not allowed to this register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 162 0011 div. ext. xtal osc. 0100 freq. mod. PLL 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 163 ME_GS register matches the configuration programmed in the respective ME_<mode>_MC register. NOTE It is recommended that software poll the S_MTRANS bit in the ME_GS register after requesting a transition to HALT, STOP, or STANDBY modes. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 164 This mode has a predefined configuration, and the 16 MHz int. RC osc. is selected as the system clock. 8.4.2.2 DRUN mode The device enters this mode on the following events. • Automatically from RESET mode after completion of the reset sequence MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 165 This mode is intended to be used by software to: • Assess the severity of the cause of failure and then to either — Reinitialize the device via the DRUN mode, or MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 166 8.4.2.6 HALT mode The device enters this mode on the following events: • From one of the RUN0…3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with 1000. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 167 In many cases of mode transition, not all steps need to be executed based on the mode control information, and some steps may not be valid according to the mode definition itself. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 168   CFLASH normal normal normal normal normal low-power power- power- down down      DFLASH normal normal normal normal normal low-power power- power- down down   MVREG MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 169 The clocks to the processor and system memories are unaffected for all transitions between software running modes including DRUN, RUN0…3, and SAFE. CAUTION Clocks to the whole device including the processor and system memories can be disabled in TEST mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 170 It is illegal to switch the flashes from low-power mode to power-down mode and from power-down mode to low-power mode. The MC_ME, however, does not prevent this nor does it flag it. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 171 8-13. A  An overview of system clock source selection possibilities for each mode is shown in Table indicates that a given clock source is selectable for a given mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 172 S_MVR of the ME_GS register. This step is required only during the entry of low-power modes like HALT and STOP. This step is executed only after completing the following processes: • Flash switch-off MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 173 Software can monitor the mode transition status by reading the S_MTRANS bit of the ME_GS register. The mode transition latency can differ from one mode to another depending on the resources’ availability before the new mode request and the target mode’s requirements. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 174 Memory Clock Disable FLASH Power Domain Switch-Off Outputs -Off Switch-Off Switch-Off Target STANDBY Clock sources Main VREG Request STANDBY Switch-Off Switch-Off S_MTRANS = 0 Current Mode Update Figure 8-16. MC_ME transition diagram MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 175 If some of the device modes are disabled as programmed in the ME_ME register, their respective configurations are considered reserved, and any access to the ME_MCTL register with those values results in an invalid mode transition request. When such a disabled mode is requested, the MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 176 Chapter 9, Reset Generation Module (MC_RGM), for details on how to clear a SAFE mode request). If the system is already in SAFE mode, any new SAFE mode request by the MC_RGM MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 177 HALT and STOP in order to avoid the same event requesting the exit of these low-power modes. 8.4.6 Application example Figure 8-17 shows an example application flow for requesting a mode change and then waiting until the mode transition has completed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 178 Stop timer Write ME_MCTL with current or mode change DONE SAFE mode and key Write ME_MCTL with current or SAFE mode and inverted key Figure 8-17. MC_ME application example flow diagram MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 179 The reset sequencer is a state machine that controls the different phases (PHASE0, PHASE1, PHASE2, PHASE3, and IDLE) of the reset sequence and control the reset signals generated in the system. Figure 9-1 shows the MC_RGM block diagram. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 180 Signalling of reset events after each reset sequence (reset status flags) • Conversion of reset events to SAFE mode or interrupt request eventsChapter 8, Mode Entry Module (MC_ME) • Short reset sequence configuration MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 181 (RGM_FERD), and Section 9.3.1.5, Functional Event Alternate Request Register (RGM_FEAR), for functional resets). External signal description The MC_RGM interfaces to the reset pin RESET and the boot mode pins PA[8] and PA[9]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 182 Any access to unused registers as well as write accesses to read-only registers will: • Not change register content • Cause a transfer error Table 9-2. MC_RGM Memory Map 0xC3FE RGM_ _4000 FES / RGM_ W w1c W w1c MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 183 The bytes are ordered according to big endian. For example, the RGM_STDBY register may be accessed as a word at address 0xC3FE_4018, as a half-word at address 0xC3FE_401A, or as a byte at address 0xC3FE_401B. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 184 1 A power-on event has occurred NOTE The F_POR flag is also set when a low-voltage is detected on the 1.2 V supply, even if the low voltage is detected after power-on has completed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 185 0 An external reset event triggers a reset sequence 1 An external reset event generates a SAFE mode request 9.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) Address 0xC3FE_4006 Access: Read Figure 9-5. Destructive Event Reset Disable Register (RGM_DERD) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 186 This register defines an alternate request to be generated when a reset on a destructive event has been disabled. The alternate request can be either a SAFE mode request to MC_ME or an interrupt request to the system. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 187 This register enables the generation of an external reset on functional reset. It can be accessed in read/write in either supervisor mode or test mode. It can be accessed in read in user mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 188 The state machine used to produce the reset sequence is shown in Figure 9-10. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 189 RESET released IDLE Figure 9-10. MC_RGM State Machine Figure 9-11 describes how the device behaves during the startup. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 190 All enabled, non-shortened functional resets have been processed • A minimum of 10 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last enabled external or non-shortened functional reset event MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 191 An enabled destructive reset will trigger a reset sequence starting from the beginning of PHASE0. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 192 The MC_RGM provides alternative events to be generated on reset source assertion. When a reset source is asserted, the MC_RGM normally enters the reset sequence. Alternatively, it is possible for each reset MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 193 RESET is asserted. RESET can be asserted as a consequence of the internal reset generation. This will force re-sampling of the boot mode pins. (See Table 9-11 details.) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 194 Chapter 9 Reset Generation Module (MC_RGM) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 195 #0 are in the power-down state. In addition, the MC_PCU acts as a bridge for mapping the VREG peripheral to the MC_PCU address space. Figure 10-1 shows the MC_PCU block diagram. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 196 Power states updating on each mode change and on system wakeup • A handshake mechanism for power state changes thus guaranteeing operable voltage 10.1.3 Modes of operation The MC_PCU is available in all device modes. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 197 Power Domain Status word read read read on page 202 _8040 Register NOTE Any access to unused registers as well as write accesses to read-only registers will: • Not change register content MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 198 Table 10-2. MC_PCU memory map 0xC3FE PCU_PCONF0 _8000 0xC3FE PCU_PCONF1 _8004 0xC3FE PCU_PCONF2101 _8008 2456789 0xC3FE PCU_PCONF1012 _800C 3456789 0xC3FE _800123 048C reserved … 0xC3FE _803C 0xC3FE PCU_PSTAT _8040 0x044 … reserved 0x07C MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 199 Table 10-3. Power Domain Configuration Register field descriptions Field Description Power domain control during RESET mode 0 Power domain off 1 Power domain on TEST Power domain control during TEST mode 0 Power domain off 1 Power domain on MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 200 This register defines for power domain #1 whether it is on or off in each device mode. The bit field description is the same as in Table 10-3. As the platform, clock generation, and mode control reside in MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 201 Table 10-3. 10.3.1.4 Power Domain #2…10123456789 Configuration Registers (PCU_PCONF2…10123456789) Address 0xC3FE_8008 Access: User read/write, Supervisor read/write, Test read/write Reset Reset Figure 10-5. Power Domain #2 Configuration Register (PCU_PCONF2) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 202 The MC_PCU controls all available power domains on a device mode basis. The PCU_PCONFn registers specify during which system/user modes a power domain is powered up. The power state for each individual power domain is reflected by the bits in the PCU_PSTAT register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 203 During the power-down phase, clocks are disabled and the reset is asserted, resulting in a loss of all information for this power domain. Then the power domain is disconnected from the power supply (power-down state). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 204 #1. During the power down phase, clocks are disabled and reset is asserted resulting in a loss of all information for this power domain. Then the power domain is disconnected from the power supply (power-down state). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 205 Data in the memories is retained. 10.5 Initialization information To initialize the MC_PCU, the registers PCU_PCONF2…3 should be programmed. After programming is done, those registers should no longer be changed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 206 Additional power is required during restoring the information (for example, in the platform). Care should be taken that the time during which the SoC is operating in STANDBY mode is significantly longer than the required time for restoring the information. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 207 The LPREG generates power for the device in the STOP mode, providing the output supply of 1.2 V. It always sees the minimum external capacitance. The control part of the regulator can be used to disable the low power regulator. It is managed by MC_ME. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 208 The VREG digital interface also holds control register to mask 5 V LVD status coming from the voltage regulator at the power-up. 1. See section “Voltage monitor electrical characteristics” of the data sheet for detailed information about this voltage value. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 209 3. BV (high voltage external power supply for voltage regulator module) — This must be provided externally through VDD_BV_/VSS_BV power pins. Voltage values should be aligned with . Refer to data sheet for details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 210 1. Regulator ground is separated from oscillator ground and shorted to the LV ground through star routing 2. During production test, it is also possible to provide the VDD_LV externally through pins by configuring regulator in bypass mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 211 CFLASH platform 330nF 330nF DFLASH 48 KB RAM Vdd5_dlf (PD2) Peripheral Peripheral VDD12 330nF ADC0 / AVSSref ADC1 AVSSsupply VDD_LV_COR VDD_LV_BKP VDD_LV_FLA1 VDD_LV_FLA0 AVDDsupply VDD_LV_BKP domain AVDDref Figure 11-2. Power domain organization MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 212 Chapter 11 Voltage Regulators and Power Supplies This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 213 PCR19 LIN0RX EIF11    WKPU12 PCR39 LIN1RX EIF12    WKPU13 PCR41 LIN2RX EIF13    WKPU14 PE11 PCR75 LIN3RX EIF14   WKPU15 PF11 PCR91 LIN4RX EIF15 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 214 (such as CAN and LINFlex Rx) that could be used to wake up the microcontroller. DSPI pins are not included because DSPI would typically be used in master mode. WISR, IRER, WRER, WIFEER, WIFEEF, WIFER, WIPUER Port not required to use timer functions. Unavailable WKPU pins must use internal pullup enabled using WIPUER. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 215 — Four system interrupt vectors for as many as 29 interrupt sources — Analog glitch filter per each wakeup line — Independent interrupt mask — Edge detection — Configurable system wakeup triggering from all interrupt sources — Configurable pullup • On-chip wakeup support MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 216 Wakeup Request Enable Register (WRER) on page 220 0x20 – 0x27 Reserved 0x28 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) on page 220 0x2C Wakeup/Interrupt Falling-Edge Event Enable Register (WIFEER) on page 221 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 217 NMI occurred while the last one was not yet serviced. If enabled (NREE0 or NFEE0 set), NOVF0 causes an interrupt request. 1 An overrun has occurred on NMI input 0 No overrun has occurred on NMI input MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 218 NMI Falling-edge Events Enable 1 Falling-edge event is enabled 0 Falling-edge event is disabled NFE0 NMI Filter Enable Enable analog glitch filter on the NMI pad input. 1 Filter is enabled 0 Filter is disabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 219 Also, the configuration registers for the external interrupts/wakeups do not have corresponding bits. 12.4.5 Interrupt Request Enable Register (IRER) This register is used to enable the interrupt messaging from the wakeup/interrupt pads to the interrupt controller. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 220 12.4.7 Wakeup/Interrupt Rising-Edge Event Enable Register (WIREER) This register is used to enable rising-edge triggered events on the corresponding wakeup/interrupt pads. NOTE The RTC_API can only be configured on the rising edge. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 221 Wakeup/Interrupt Filter Enable Register (WIFER) This register is used to enable an analog filter on the corresponding interrupt pads to filter out glitches on the inputs. NOTE There is no analog filter for the RTC_API. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 222 Field Description IPUE[x] External Interrupt Pullup Enable x 1 Pullup is enabled 0 Pullup is disabled 12.5 Functional description 12.5.1 General This section provides a complete functional description of the Wakeup Unit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 223 Mode/ Pwr Ctl Destination Wakeup Enable Flag Overrun Edge Detect Glitch Filter NMI Configuration Register (NCR) Figure 12-11. NMI pad diagram 12.5.2.1 NMI management MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 224 0 through N – 1, the next is for N through N + M – 1, and so forth. Figure 12-12 for an overview of the external interrupt implementation for the example of four interrupt vectors with as many as eight external interrupt sources each. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 225 Each external interrupt supports an individual flag that is held in the flag register (WISR). The bits in the WISR[EIF] field are cleared by writing a 1 to them; this prevents inadvertent overwriting of other flags in the register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 226 In order to allow software to determine the wakeup source at one location, on-chip wakeups are reported along with external wakeups in the WISR register (see Figure 12-4 for details). Enabling and clearing of these wakeups are done via the on-chip wakeup source’s own registers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 227 — 10-bit compare value to support wakeup intervals of 1.0 ms to 1 second — Compare value changeable while counter is running • Configurable interrupt for RTC match, API match, and RTC rollover • Configurable wakeup event for RTC match, API match, and RTC rollover MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 228 22:31 API wakeup Reserved sync FIRC SIRC APIF 32-bit counter SXOSC APIIE interrupt 10:21 reset RTCVAL RTC wakeup sync sync RTCF RTCIE RTC interrupt ROVRF RTCIE ROVREN Figure 13-1. RTC/API block diagram MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 229 Figure 13-2. Clock gating for RTC clocks 13.3 Device-specific information For MPC5606BK, the device specific information is the following: • SXOSC, FIRC, and SIRC clocks are provided as counter clocks for the RTC. Default clock on reset is SIRC divided by 4.
Page 230 Table 13-2. RTCSUPV field descriptions Field Description SUPV RTC Supervisor Bit 0 All registers are accessible in both user as well as supervisor mode. 1 All other registers are accessible in supervisor mode only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 231 The counter freezes on entering the debug mode on the last valid count value if the FRZEN bit is set. After coming out of the debug mode, the counter starts from the frozen value. 0 Counter does not freeze in debug mode. 1 Counter freezes in debug mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 232 APIVAL to the RTC clock, and APIVAL + 1 cycles for subsequent occurrences. After that, interrupts are periodic in nature. The minimum supported value of APIVAL is 4. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 233 The ROVRF bit indicates that the RTC has rolled over from 0xffff_ffff to 0x0000_0000. ROVRF is cleared by writing a 1 to ROVRF. 1 RTC has rolled over 0 RTC has not rolled over MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 234 All the flags and counter values are synchronized with the system clock. It is assumed that the system clock frequency is always more than or equal to the rtc_clk used to run the counter. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 235 If there is a match while in low power mode, then the API will first generate a wakeup request to force a wakeup into normal operation, then the APIF flag will be set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 236 Chapter 13 Real Time Clock / Autonomous Periodic Interrupt (RTC/API) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 237 User selectable CAN Rx sample port [CAN0RX–CAN5RX] • 16 MHz fast internal RC oscillator clock • 5-bit clock prescaler • Configurable trigger mode (immediate, next frame) • Flexible samples processing by software • Very low power consumption MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 238 This bit indicates the current clock (xmem_ck) for sample registers 0: ipg_clk_s is currently xmem_ck 1: RC_CLK is currently xmem_ck MODE 0:Skip the first frame and sample and store the second frame (SF_MODE) 1:Sample and store the first frame (FF_MODE) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 239 CAN identifier sent at 500 kbit/s. Therefore the first identifier is ignored and the sampling is performed on the first falling edge of after interframe space. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 240 One Rx port can be selected per sampling routine. The port to be sampled is selected by CAN_RX_SEL. Table 14-3. Internal multiplexer correspondence CAN_RX_SEL Rx selected CAN0RX on PB[1] CAN1RX on PC[11] CAN2RX on PE[9] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 241 = 8 µs Eqn. 14-1 To achieve 8 samples per bit Sample period= 8/8 µs = 1 µs BRP = 1 µs/62.5 ns = 16. Thus in this case BRP = 01111 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 242 Chapter 14 CAN Sampler This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 243 ——— Core platform modules ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 244 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 245 Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 246 Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 247 The following is a list of some of the key features of the e200z0h core: • 32-bit Power Architecture VLE-only programmer’s model • Single issue, 32-bit CPU • Implements the VLE APU for reduced code footprint • In-order execution and retirement MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 248 32-bit AU for arithmetic and comparison operations • 32-bit LU for logical operations • 32-bit priority encoder for count leading zeros function • 32-bit single cycle barrel shifter for shifts and rotates MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 249 (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). 1. Advanced Microcontroller Bus Architecture 2. Advanced High Performance Bus MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 250 Significant Bit) to 31 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 251 1 - These e200-specific registers may not be DVC2 SPR 319 supported by other Power Architecture processors. 2 - Optional registers defined by the Power Architecture technology 3 - Read-only registers Figure 15-2. e200z0 SUPERVISOR Mode Program Model SPRs MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 252 Chapter 15 e200z0h Core This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 253 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture includes a DMA engine that performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 254 — An inner data transfer loop defined by a minor byte transfer count — An outer data transfer loop defined by a major iteration count • Channel service request via one of three methods: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 255 EDMA_CERQR — eDMA clear enable request register on page 264 0x001A EDMA_SEEIR — eDMA set enable error interrupt register on page 264 0x001B EDMA_CEEIR — eDMA clear enable error interrupt register on page 265 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 256 TCD00 — eDMA transfer control descriptor 00 on page 271 0x1020 TCD01 — eDMA transfer control descriptor 01 on page 271 0x1040 TCD02 — eDMA transfer control descriptor 02 on page 271 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 257 (EDMA_CPRn))). In round-robin arbitration mode, the channel priorities are ignored and the channels are cycled through, from channel 15 down to channel 0, without regard to priority. Figure 16-2 Table 16-2 for the EDMA_CR definition. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 258 HALT Halt DMA Operations Normal operation. 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution will resume when the HALT bit is cleared. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 259 DMA engine with the current source address, destination address, and minor loop byte count at the point of the fault. If a bus error occurs on the last read prior to beginning the write sequence, the write will MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 260 TCD.saddr is inconsistent with TCD.ssize. Source Offset Error No source offset configuration error. 1 The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff is inconsistent with TCD.ssize. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 261 Both the eDMA request input signal and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the eDMA enable request flag does not affect a channel service request made through software or a linked channel request. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 262 Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. See Figure 16-5 Table 16-5 for the EDMA_EEIRL definition. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 263 Figure 16-6. DMA Set Enable Request (EDMA_SERQR) Register Table 16-6. EDMA_SERQR field descriptions Field Description SERQ Set Enable Request 0–15 Set the corresponding bit in EDMA_ERQRL 64–127 Set all bits in EDMA_ERQRL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 264 Figure 16-8. DMA Set Enable Error Interrupt (EDMA_SEEIR) Register Table 16-8. EDMA_SEEIR field descriptions Name Description SEEI Set Enable Error Interrupt 0–63 Set the corresponding bit in EDMA_EEIRL 64–127 Set all bits in EDMA_EEIRL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 265 Figure 16-10. DMA Clear Interrupt Request (EDMA_CIRQR) Fields Table 16-10. EDMA_CIRQR field descriptions Field Description CINT[0:6] Clear Interrupt Request 0–63 Clear the corresponding bit in EDMA_IRQRL 64–127 Clear all bits in EDMA_IRQRL MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 266 Figure 16-12. DMA Set START Bit (EDMA_SSBR) Register Table 16-12. EDMA_SSBR field descriptions Field Description SSRT Set START Bit (Channel Service Request) 0–63 Set the corresponding channel’s TCD.start 64–127 Set all TCD.start bits MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 267 The EDMA_CIRQR is provided so the interrupt request for a single channel can be cleared without performing a read-modify-write sequence to the EDMA_IRQRL. See Figure 16-14 Table 16-14 for the EDMA_IRQL definition. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 268 The EDMA_CER is provided so the error indicator for a single channel can be cleared. See Figure 16-15 Table 16-15 for the EDMA_ERL definition. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 269 This view into the hardware request signals may be used for debug purposes. Figure 16-16 Figure 16-16 for the EDMA_HRSL definition. Offset: 0x0034 Access: Read/write RESET: RESET: Figure 16-16. DMA Hardware Request Status (EDMA_HRSL) Register MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 270 Figure 16-17 Table 16-17 for the EDMA_CPRn definition. Offset: 0x0100 + n Access: Read/write GRPPRI CHPRI RESET: = defaults to channel number (n) after reset Figure 16-17. DMA Channel n Priority (EDMA_CPRn) Register MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 271 0x1000 (32 × n) 0x0018 Last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 × n)+0x001C Beginning major iteration count (biter) Channel control/status Figure 16-18 Table 16-19 define the fields of the TCDn structure. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 272 The TCD structures for the eDMA channels shown in Figure 16-18 implemented in internal SRAM. These structures are not initialized at reset; therefore, all channel TCD parameters must be initialized by the application code before activating that channel. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 273 If the major iteration count is completed, additional processing is performed. Note: The NBYTES value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 GB transfer. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 274 128–159 / DADDR Destination address. Memory address pointing to the destination data. 0x10 [0:31] [0:31] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 275 BITER and CITER should be 0x0001. 176–191 / DOFF Destination address signed Offset. Sign-extended offset applied to the 0x14 [16:31] [0:15] current destination address to form the next-state value as each destination write is completed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 276 As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Note: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 277 NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCD.DONE bit is set. 0 The channel-to-channel linking is disabled. 1 The channel-to-channel linking is enabled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 278 The fields implemented at 0x8 depend on whether EDMA_CR(EMLM) is set to 0 or 1. Refer to Table 16-2. 16.4 Functional description This section provides an overview of the microarchitecture and functional operation of the eDMA block. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 279 A minor loop interaction is defined as the number of bytes to transfer (nbytes) divided by the transfer size. Transfer size is defined as: if (SSIZE < DSIZE) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 280 DMA engine address path channel{x,y} registers. The TCD memory is organized 64 bits in width to minimize the time needed to fetch the activated channel’s descriptor and load it into the eDMA engine address path channel{x,y} registers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 281 This source read/destination write processing continues until the inner minor byte count has been transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 282 TCD from memory using the scatter-gather address pointer included in the descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 16-21. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 283 After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The DMA engine will read the entire TCD, including the MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 284 DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (biter). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 285 For all error types other than channel-priority errors, the channel number causing the error is recorded in the EDMA_ESR. If the error source is not removed before the next activation of the problem channel, the error will be detected and recorded again. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 286 16.5.4.2 Round-robin channel arbitration In this mode, channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the assigned channel priority levels. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 287  first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004)  second iteration of the minor loop e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b) f) write_word(0x2008)  third iteration of the minor loop MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 288 5. The source to destination transfers are executed as follows: a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003) b) write_word(0x2000)  first iteration of the minor loop c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007) d) write_word(0x2004)  second iteration of the minor loop MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 289 (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 2 byte (16-byte) size queue. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 290 4. TCD.START = 0, TCD.ACTIVE = 0, TCD.DONE = 1 (channel has completed the major loop and is idle). For both activation types, the major loop complete status is explicitly indicated via the TCD.DONE bit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 291 TCD.CITER value = 0x4 TCD.MAJOR.E_LINK = 1 TCD.MAJOR.LINKCH = 0x7 will execute as: 1. Minor loop done  set channel 12 TCD.START bit 2. Minor loop done  set channel 12 TCD.START bit MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 292 The coherency model in Table 16-24 is recommended when executing a dynamic channel link request. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 293 Method 1 (channel not using major loop channel linking) For a channel not using major loop channel linking, the coherency model in Table 16-25 may be used for a dynamic scatter/gather request. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 294 • If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). • If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 295 — 12 channels with normal capability • Capability to assign each channel router to one of 59 possible peripheral DMA sources, four always enabled sources, or one always disabled source • Three modes of operation: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 296 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, CHCONFIG0 through CHCONFIG3 are accessible by a 32-bit read/write to address Base + 0x00, but performing a 32-bit access to address Base + 0x01 is illegal. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 297 NOTE Setting multiple CHCONFIG registers with the same Source value results in unpredictable behavior. NOTE Before changing the trigger or source settings an eDMA channel must be disabled via the CHCONFIGn[ENBL] bit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 298 DMA_MUX Source #23 eMIOS 1 EMIOS1_CH9 DMA_MUX Source #24 eMIOS 1 EMIOS1_CH17 DMA_MUX Source #25 eMIOS 1 EMIOS1_CH18 DMA_MUX Source #26 eMIOS 1 EMIOS1_CH25 DMA_MUX Source #27 eMIOS 1 EMIOS1_CH26 DMA_MUX Source #28 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 299 DMA_MUX Source #52 — — DMA_MUX Source #53 — — DMA_MUX Source #54 — — DMA_MUX Source #55 — — DMA_MUX Source #56 — — DMA_MUX Source #57 — — DMA_MUX Source #58 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 300 (PIT); as such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. Please see Section 27.5, Periodic Interrupt Timer (PIT), for more information on this topic. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 301 This is illustrated Figure 17-4. Periph Request Trigger DMA Request Figure 17-4. DMA_MUX channel triggering: Normal operation MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 302 A more detailed description of the capability of each trigger (such as resolution, or range of values) may be found in Chapter 27, Timers. 17.7.2 eDMA channels with no triggering capability Channels 4–15 of the DMA_MUX provide the normal routing functionality as described in Section 17.3, Modes of operation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 303 2. Clear the ENBL and TRIG bits of the eDMA channel. 3. Ensure that the eDMA channel is properly configured in the eDMA. The eDMA channel may be enabled at this point. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 304 In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8 bits */ volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); In File main.c: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 305 0xFC084000/* Example only ! */ /* Following example assumes char is 8 bits */ volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); In File main.c: #include "registers.h" *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87; MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 306 Chapter 17 eDMA Channel Multiplexer (DMA_MUX) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 307 — Ability to modify the ISR or task priority; modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. • Low latency – 3 clocks from receipt of interrupt request from peripheral to interrupt request to processor MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 308 Real Time Counter (RTC/API) System Integration Unit Lite (SIUL) WKPU MC_ME MC_RGM FXOSC SXOSC ADC_0 ADC_1 FlexCAN_0 FlexCAN_1 FlexCAN_2 FlexCAN_3 FlexCAN_4 FlexCAN_5 LINFlex_0 LINFlex_1 LINFlex_2 LINFlex_3 LINFlex_4 LINFlex_5 LINFlex_6 LINFlex_7 DSPI_0 DSPI_1 DSPI_2 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 309 Non-Memory Mapped Logic Figure 18-1. INTC block diagram 18.4 Modes of operation 18.4.1 Normal mode In normal mode, the INTC has two handshaking modes with the processor: software vector mode and hardware vector mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 310 In this case, PRI in the associated INTC_CPR is updated with the new priority, and the associated LIFO is neither pushed or popped. 18.4.1.3 Debug mode The INTC operation in debug mode is identical to its operation in normal mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 311 16 bits to the middle 2 bytes, and aligned 32 bits. Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided that the access does not cross a 32-bit boundary. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 312 Section 18.4, Modes of operation, for the details of the handshaking with the processor in each mode. 0 Software vector mode 1 Hardware vector mode 18.5.2.2 INTC Current Priority Register for Processor (INTC_CPR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 313 Table 18-5. PRI values Meaning 1111 Priority 15—highest priority 1110 Priority 14 1101 Priority 13 1100 Priority 12 1011 Priority 11 1010 Priority 10 1001 Priority 9 1000 Priority 8 0111 Priority 7 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 314 Figure 18-4. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 0 Offset: 0x0010 Access: User read/write VTBA[19:4] Reset INTVEC VTBA[3:0] Reset Figure 18-5. INTC Interrupt Acknowledge Register (INTC_IACKR) when INTC_MCR[VTES] = 1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 315 INTC_EOIR are ignored. The values and sizes written to this register neither update the INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR. Reading the INTC_EOIR has no effect on the LIFO. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 316 The software set/clear interrupt registers support the setting or clearing of software configurable interrupt request. These registers contain eight independent sets of bits to set and clear a corresponding flag bit by MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 317 PRI233 Reset Reset Figure 18-10. INTC Priority Select Register 232–233 (INTC_PSR[232:233]) Table 18-8. INTC_PSR0_3–INTC_PSR232_233 field descriptions Field Description Priority Select PRIx selects the priority for interrupt requests. See Section 18.6, Functional description. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 318 INTC_PSR204_207 0x010C INTC_PSR88_91 0x0098 INTC_PSR208_211 0x0110 INTC_PSR92_95 0x009C INTC_PSR212_215 0x0114 INTC_PSR96_99 0x00A0 INTC_PSR216_219 0x0118 INTC_PSR100_103 0x00A4 INTC_PSR220_223 0x011C INTC_PSR104_107 0x00A8 INTC_PSR224_227 0x0120 INTC_PSR108_111 0x00AC INTC_PSR228_231 0x0124 INTC_PSR112_115 0x00B0 INTC_PSR232_233 0x0128 INTC_PSR116_119 0x00B4 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 319 — 0x0070 Reserved Core — 0x0080 System call Core — 0x0090 Unused Core — 0x00F0 Debug Core — 0x0100 1792 Unused Core Section B (On-Platform Peripherals) 0x0800 Software configurable flag 0 Software MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 320 0x0858 Channel 11 eDMA 0x085C Channel 12 eDMA 0x0860 Channel 13 eDMA 0x0864 Channel 14 eDMA 0x0868 Channel 15 eDMA 0x086C Reserved 0x0870 Timeout 0x0874 Reserved 0x0878 Match on channel 0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 321 Invalid Mode Interrupt MC_ME 0x08D8 Invalid Mode Config MC_ME 0x08DC Reserved 0x08E0 Functional and destructive reset alternate MC_RGM event interrupt (ipi_int) 0x08E4 FXOSC counter expired (ipi_int_osc) FXOSC 0x08E8 Reserved 0x08EC PITimer Channel 0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 322 0x093C LINFlex_RXI LINFlex_0 0x0940 LINFlex_TXI LINFlex_0 0x0944 LINFlex_ERR LINFlex_0 0x0948 ADC_EOC ADC_1 0x094C Reserved 0x0950 ADC_WD ADC_1 0x0954 FlexCAN_ESR[ERR_INT] FlexCAN_1 0x0958 FlexCAN_ESR_BOFF | FlexCAN_1 FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 0x095C Reserved 0x0960 FlexCAN_BUF_00_03 FlexCAN_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 323 FlexCAN_2 0x09B4 FlexCAN_BUF_04_07 FlexCAN_2 0x09B8 FlexCAN_BUF_08_11 FlexCAN_2 0x09BC FlexCAN_BUF_12_15 FlexCAN_2 0x09C0 FlexCAN_BUF_16_31 FlexCAN_2 0x09C4 FlexCAN_BUF_32_63 FlexCAN_2 0x09C8 DSPI_SR[TFUF] DSPI_2 DSPI_SR[RFOF] 0x09CC DSPI_SR[EOQF] DSPI_2 0x09D0 DSPI_SR[TFFF] DSPI_2 0x09D4 DSPI_SR[TCF] DSPI_2 0x09D8 DSPI_SR[RFDF] DSPI_2 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 324 Reserved 0x0A2C Reserved 0x0A30 Reserved 0x0A34 EMIOS_GFR[F0,F1] eMIOS_0 0x0A38 EMIOS_GFR[F2,F3] eMIOS_0 0x0A3C EMIOS_GFR[F4,F5] eMIOS_0 0x0A40 EMIOS_GFR[F6,F7] eMIOS_0 0x0A44 EMIOS_GFR[F8,F9] eMIOS_0 0x0A48 EMIOS_GFR[F10,F11] eMIOS_0 0x0A4C EMIOS_GFR[F12,F13] eMIOS_0 0x0A50 EMIOS_GFR[F14,F15] eMIOS_0 0x0A54 EMIOS_GFR[F16,F17] eMIOS_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 325 EMIOS_GFR[F26,F27] eMIOS_1 0x0AAC EMIOS_GFR[F28,F29] eMIOS_1 0x0AB0 EMIOS_GFR[F30,F31] eMIOS_1 0x0AB4 FlexCAN_ESR FlexCAN_3 0x0AB8 FlexCAN_ESR_BOFF | FlexCAN_3 FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 0x0ABC Reserved 0x0AC0 FlexCAN_BUF_0_3 FlexCAN_3 0x0AC4 FlexCAN_BUF_4_7 FlexCAN_3 0x0AC8 FlexCAN_BUF_8_11 FlexCAN_3 0x0ACC FlexCAN_BUF_12_15 FlexCAN_3 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 326 LINFlex_RXI LINFlex_5 0x0B20 LINFlex_TXI LINFlex_5 0x0B24 LINFlex_ERR LINFlex_5 0x0B28 FlexCAN_ESR FlexCAN_5 0x0B2C FlexCAN_ESR_BOFF | FlexCAN_5 FlexCAN_Transmit_Warning | FlexCAN_Receive_Warning 0x0B30 Reserved 0x0B34 FlexCAN_BUF_0_3 FlexCAN_5 0x0B38 FlexCAN_BUF_4_7 FlexCAN_5 0x0B3C FlexCAN_BUF_8_11 FlexCAN_5 0x0B40 FlexCAN_BUF_12_15 FlexCAN_5 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 327 0x0BA0 Reserved 0x0BA4 32KXOSC counter expired SXOSC 18.6.1 Interrupt request sources The INTC has two types of interrupt requests, peripheral and software configurable. These interrupt requests can assert on any clock cycle. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 328 The priority arbitrator subblock for each processor compares all the priorities of all of the asserted interrupt requests assigned to that processor, both peripheral and software configurable. The output of the priority arbitrator subblock is the highest of those priorities assigned to a given processor. Also, any interrupt MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 329 0s if it is popped more times than it is pushed. Therefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty LIFO. The LIFO is not memory mapped. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 330 This next instruction is part of the preempted ISR or the interrupt exception handler’s prolog or epilog. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 331 The handshaking near the end of the interrupt exception handler, that is the writing to the INTC_EOIR, is the same as in software vector mode. Refer to Section 18.6.3.1.2, End of interrupt exception handler. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 332 PRI in INTC_CPR to zero enable processor recognition of interrupts 18.7.2 Interrupt exception handler These example interrupt exception handlers use Power Architecture assembly code. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 333 This interrupt exception handler is useful with processor and system bus implementations that support a hardware vector. This example assumes that each interrupt_exception_handlerx only has space for four instructions, and therefore a branch to interrupt_exception_handler_continuedx is needed. interrupt_exception_handlerx: b interrupt_exception_handler_continuedx# 4 instructions available, branch to continue MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 334 Since the ISRs are outside the control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler, perhaps after executing another ISR. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 335 INTC_EOIR. ISR108 completes. Interrupt exception handler writes to INTC_EOIR. RTOS continues execution. ISR108 executes for peripheral interrupt request 100 because the first eight ISRs are for software configurable interrupt requests. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 336 ISR to the deadline, not from the time of the request for the ISR to the next request for it. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 337 ISRs on the other processors. One application is that one processor wants to command another processor to perform a piece of work and the initiating processor does not need to use MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 338 Their PRIx values in the INTC Priority Select Registers MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 339 When the examination is complete, the LIFO can be restored using this code sequence: push_lifo: load stacked PRI value and store to INTC_CPR load INTC_IACKR if stacked PRI values are not depleted, branch to push_lifo MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 340 Chapter 18 Interrupt Controller (INTC) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 341 The crossbar of MPC5606BK is the same as the one of all other PPC55xx and PPC56xx products except that it cannot be configured by software and that it has a hard-wired configuration.
Page 342 The main goal of the XBAR is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. To maximize data throughput, it is essential to keep arbitration delays to a minimum. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 343 If the slave port is currently servicing another master of a higher priority, then the master gains control of the slave port after MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 344 (if any). The slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 345 When the master accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalty is incurred for each access request to the slave port made by another master port. All other masters pay a one clock penalty. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 346 Chapter 19 Crossbar Switch (XBAR) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 347 To enable monitoring of an output pad value, the pad can be configured as both output and input so the actual pad value can be read back and compared with the expected value. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 348 149 GPIOs in 176-pin LQFP and 208 BGA, as many as 121 GPIOs in 144-pin LQFP and as many as 77 GPIOs in 100-pin LQFP 24 EIRQs in 144-pin LQFP, 176-pin LQFP and 208 BGA; as many as 20 EIRQs in 100-pin LQFP Figure 20-1. System Integration Unit Lite block diagram MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 349 Most, but not all GPIO pads can be configured as inputs or outputs but some, e.g., analog pins with GPIO function, are only configurable as inputs. PE[14], PF[15], PG[1], and PG[8] not available in 100-pin LQFP 1.Some device pins, e.g., analog pins, do not have both input and output functionality. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 350 SIUL_IREER or the SIUL_IFEER register. 1. GPIO[0–26], GPIO[28–59], and GPIO[61–122] in 144-pin LQFP; GPIO[0–26], GPIO[28–59], GPIO[61–76], and GPIO[121–122] in 100-pin LQFP 2. EIRQ[0:11] plus EIRQ[16:23] in 100-pin LQFP MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 351 367 0x0C14–0x0C3F Reserved 0x0C40–0x0C50 Parallel GPIO Pad Data In Registers (PGPDI0 – PGPDI4) on page 368 0x0C54–0x0C7F Reserved 0x0C80–0x0CA4 Masked Parallel GPIO Pad Data Out Register on page 369 (MPGPDO0–MPGPDO9) 0x0CA8–0x0FFF Reserved MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 352 Pad Selection for Multiplexed Inputs Registers (PSMI0_3–PSMI60_63) • Interrupt Filter Maximum Counter Registers (IFMC0–IFMC23). Note that only IFMC[0:15] can be protected. • Interrupt Filter Clock Prescaler Register (IFCPR) Chapter 32, Register Protection, for more details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 353 0b10001: 176-pin LQFP MAJOR_MASK Major Mask Revision Counter starting at 0x0. Incremented each time there is a resynthesis. MINOR_MASK Minor Mask Revision Counter starting at 0x0. Incremented each time a mask change is done. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 354 For the full part number this field needs to be combined with MIDR1[PARTNUM[15:0]]. Data Flash present 0 No Data Flash is present 1 Data Flash is present 20.5.3.3 Interrupt Status Flag Register (ISR) This register holds the interrupt flags. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 355 This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRER[x]), EIF[x] causes an interrupt request. 0 No interrupt event has occurred on the pad 1 An interrupt event as defined by IREER[x] and IFEER[x] has occurred MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 356 This register is used to enable rising-edge triggered events on the corresponding interrupt pads. Offset:0x0028 Access: User read/write IREE[23:16] Reset IREE[15:0] Reset Figure 20-6. Interrupt Rising-Edge Event Enable Register (IREER) 20 enable events in 100-pin LQFP: IREE[23:16] plus IREE[11:0] (register bits 16–19 reserved). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 357 If IREER[IREE] and IFEER[IFEE] bits are set for the same source the interrupts are triggered by both rising edge events and falling edge events. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 358 — Select the feature location from PSMI register — Set the IBE bit in the appropriate PCR • For normal GPIO (not alternate function): — Configure PCR — Read from GPDI or write to GPDO MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 359 This bit supports the overriding of the automatic deactivation of the output buffer of the associated pad upon entering SAFE mode of the device. 0 In SAFE mode, the output buffer of the pad is disabled. 1 In SAFE mode, the output buffer remains functional. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 360 CAN1_RXD signal can be selected on three different pins: PC[3], PC[11], and PF[15]. Only one can be active at a time. To select the pad to be used as input to the peripheral: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 361 10: PCR[95] PADSEL1 0x501 CAN2RX / FlexCAN_2 00: PCR[73] 01: PCR[89] PADSEL2 0x502 CAN3RX / FlexCAN_3 00: PCR[36] 01: PCR[73] 10: PCR[89] PADSEL3 0x503 CAN4RX / FlexCAN_4 00: PCR[35] 01: PCR[43] 10: PCR[95] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 362 00: PCR[6] 01: PCR[30] PADSEL17 0x511 E0UC[7] / eMIOS_0 00: PCR[7] 01: PCR[31] 10: PCR[41] PADSEL18 0x512 E0UC[10] / eMIOS_0 00: PCR[10] 01: PCR[80] PADSEL19 0x513 E0UC[11] / eMIOS_0 00: PCR[11] 01: PCR[81] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 363 01: PCR[124] PADSEL33 0x521 SIN_3 / DSPI_3 00: PCR[101] 01: PCR[139] PADSEL34 0x522 CS0_3 / DSPI_3 00: PCR[99] 01: PCR[125] 10: PCR[140] PADSEL35 0x523 SCK_4 / DSPI_4 00: PCR[109] 01: PCR[126] 10: PCR[133] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 364 E1UC[5] / eMIOS_1 00: PCR[115] 01: PCR[123] PADSEL49 0x531 E1UC[17] / eMIOS_1 00: PCR[104] 01: PCR[127] PADSEL50 0x532 E1UC[18] / eMIOS_1 00: PCR[105] 01: PCR[148] PADSEL51 0x533 E1UC[25] / eMIOS_1 00: PCR[92] 01: PCR[124] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 365 PADSEL63 not implemented 20.5.3.10 GPIO Pad Data Output Registers (GPDO0_3–GPDO148_151) These registers are used to set or clear GPIO pads. Each pad data out bit can be controlled separately with a byte access. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 366 Please see data sheet. 20.5.3.11 GPIO Pad Data Input Registers (GPDI0_3–GPDI148_151) These registers are used to read the GPIO pad data with a byte access. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 367 1 Value of the data in signal for the corresponding GPIO pad is logic high 20.5.3.12 Parallel GPIO Pad Data Out Registers (PGPDO0 – PGPDO4) MPC5606BK devices ports are constructed such that they contain 16 GPIO pins, for example PortA[0..15]. Parallel port registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be written or read in one operation, dependent on the individual pad configuration.
Page 368 Table 20-17. PGPDI0 – PGPDI4 register map Field Offset Register 0x0C40 PGPDI0 Port A Port B 0x0C44 PGPDI1 Port C Port D 0x0C48 PGPDI2 Port E Port F 0x0C4C PGPDI3 Port G Port H MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 369 0x0C8C MPGPDO3 MASK3 (Port D) MPPDO3 (Port D) 0x0C90 MPGPDO4 MASK4 (Port E) MPPDO4 (Port E) 0x0C94 MPGPDO5 MASK5 (Port F) MPPDO5 (Port F) 0x0C98 MPGPDO6 MASK6 (Port G) MPPDO6 (Port G) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 370 These registers are used to configure the filter counter associated with each digital glitch filter. NOTE For the pad transition to trigger an interrupt it must be steady for at least the filter period. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 371 This register is used to configure a clock prescaler that selects the clock for all digital filter counters in the SIUL. Offsets:0x1080 Access: User read/write Reset IFCP Reset Figure 20-14. Interrupt Filter Clock Prescaler Register (IFCPR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 372 20-15, all port accesses are identical with each read or write being performed only at a different location to access a different port width. 1.There are exceptions. Some pads, e.g., precision analog pads, are input only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 373 All of the external interrupt pads within a single group have equal priority. Figure 20-16 for an overview of the external interrupt implementation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 374 ISR[EIF] field are cleared by writing a 1 to them; this prevents inadvertent overwriting of other flags in the register. 20.7 Pin muxing For pin muxing, please see Chapter 4, Signal description. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 375 – Connections to the address phase address and attributes – Typical location is immediately downstream of the platform’s crossbar switch A simplified block diagram of the MPU module is shown in Figure 21-1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 376 — For overlapping region descriptors, priority is given to permission granting over access denying as this approach provides more flexibility to system software. See Section 21.6.2, Putting it all together and AHB error terminations, for details and Section 21.8, Application information, for an example. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 377 IPS error termination. Finally, the programming model allocates space for an MPU definition with 8 region descriptors and as many as three XBAR slave ports, like flash controller, system SRAM controller and peripheral bus. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 378 MPU RGD Alternate Access Control 5 (MPU_RGDAAC5) on page 387 0x818 MPU RGD Alternate Access Control 6 (MPU_RGDAAC6) on page 387 0x81C MPU RGD Alternate Access Control 7 (MPU_RGDAAC7) on page 387 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 379 Number of Region Descriptors This field specifies the number of region descriptors implemented in the MPU. The defined encodings include: 0000 8 region descriptors 0001 12 region descriptors 0010 16 region descriptors MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 380 Figure 21-3. MPU Error Address Register, Slave Port n (MPU_EARn) Table 21-4. MPU_EARn field descriptions Field Description EADDR Error Address This field is the reference address from slave port n that generated the access error. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 381 Error Master Number This field records the logical master number of the faulting reference. This field is used to determine the bus master that generated the access error. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 382 – – – – – – – – – – SRTADDR[10:0] Reset – – – – – – – – – – – Figure 21-5. MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 383 XBAR hmaster[3:0] signal. For the processor privilege rights, there are three flags associated with this function: {read, write, execute}. In this context, these flags follow the traditional definition: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 384 If set, this flag allows bus master 6 to perform read operations. If cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 385 (if not allowed by any other descriptor) and the access not performed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 386 If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 387 If only the access controls are being updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n) as stores to these locations do not affect the descriptor’s valid bit. The memory address therefore provides an alternate location for updating MPU_RGDn.Word2. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 388 If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 389 (if not allowed by any other descriptor) and the access not performed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 390 PID with its PIDMASK. Also the process identifier enable is take into account in this comparison so that the MPU forces the pid_hit term to be asserted in the case of AHB bus master doesn't provide its process identifier. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 391 In event of a protection error, the MPU requires two distinct actions: • Intercepting the error during the address phase (first cycle out of two) and cancelling the transaction before it is seen by the slave device MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 392 When the MPU detects an access error, the current bus cycle is terminated with an error response, and information on the faulting reference is captured in the MPU_EARn and MPU_EDRn registers. The MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 393 In any event, the processor can retrieve the captured error address and detail information by reading the MPU_E{A,D}Rn registers. Information on that error registers contain captured fault data is signaled by MPU_CESR[SPERR]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 394 Chapter 21 Memory Protection Unit (MPU) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 395 ——— Communication modules ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 396 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 397 Repeated start signal generation • Acknowledge bit generation/detection • Bus busy detection • Direct memory access Features currently not supported: • No support for general call address • Not compliant to 10-bit addressing MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 398 C module is given below in Table 22-1. The total address for each register is the sum of the base address for the I C module and the address offset for each register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 399 Slave Address. Specific slave address to be used by the I C Bus module. Note: The default mode of I C Bus is slave mode for an address match on the bus. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 400 2–0 select the shift register tap point (see Table 22-6) Table 22-4. I-Bus multiplier factor – IBC7 RESERVED Table 22-5. I-Bus prescaler divider values scl2start scl2stop scl2tap tap2tap – IBC5 (clocks) (clocks) (clocks) (clocks) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 401 22-5. The SCL Tap is used to generate the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to the change of state of SDA i.e. the SDA hold time. SCL Divider SDA Hold Figure 22-4. SDA hold time MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 402 The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL × [scl2start + (SCL_Tap – 1) × tap2tap] Eqn. 22-3 SCL Hold(stop) = MUL × [scl2stop + (SCL_Tap – 1) × tap2tap] Eqn. 22-4 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 403 SCL hold SCL hold (hex) (clocks) (clocks) (start) (stop) 1024 1152 1280 1536 1920 1280 1536 1792 2048 1022 1025 2304 1150 1153 2560 1278 1281 3072 1534 1537 3840 1918 1921 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 404 1276 1282 3072 1532 1538 3840 1916 1922 2560 1276 1282 3072 1532 1538 3584 1788 1794 4096 2044 2050 4608 2300 2306 5120 2556 2562 6144 3068 3074 7680 3836 3842 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 405 3832 3844 5120 2552 2564 6144 3064 3076 7168 1028 3576 3588 8192 1028 4088 4100 9216 1540 4600 4612 10240 1540 5112 5124 12288 2052 6136 6148 15360 2052 7672 7684 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 406 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 407 Bus busy. This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy 0 Bus is Idle MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 408 For instance, if the I C is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 409 C can request data transfers with minimal support from the CPU. DMA mode is enabled by setting bit 1 in the Control Register. The DMA interface is only valid when the I C module is configured for Master Mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 410 Two internal signals, TX request and RX request, are used to signal to a DMA controller when the I module requires data to be written or read from the data register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 411 START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 412 Each data byte must be followed by an acknowledge bit, which is signaled from the receiving device by pulling the SDA low at the ninth clock. Therefore, one complete data byte transfer needs 9 clock pulses. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 413 There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 414 Arbitration lost, Transfer Complete or IBSR register Address Detect conditions. If enabled by BIIE, the deassertion of IBB can also cause an interrupt, indicating that the bus is idle. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 415 The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 416 4. IBSR[TCF] bit will get set when transfer is complete. 5. Wait for IBSR[IBIF] to get set, then read IBSR register to determine its source: — TCF = 1, transfer is complete. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 417 (bit 0, IBSR == 1) {// or if no ACK generated clear bit 5, IBCR// generate stop condition else { IBDR = data_to_transmit// write byte of data to DATA register tx_count --// decrement counter }// return from interrupt MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 418 STOP condition, generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 419 Mode Read Data Dummy Read Generate Dummy Read Dummy Read From IBDR From IBDR Stop Signal From IBDR From IBDR And Store Figure 22-14. Flow chart of typical I C interrupt routine MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 420 Chapter 22 Inter-Integrated Circuit Bus Controller Module (I This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 421 8- or 9-bit with parity • 4-byte buffer for reception, 4-byte buffer for transmission • 8-bit counter for timeout management 23.2.3 Features common to LIN and UART • Fractional baud rate generator MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 422 Configure LIN parameters (for example, baud rate or mode) • Request transmissions • Handle receptions • Manage interrupts • Configure LIN error and timeout detection • Process diagnostic information The message buffer stores transmitted or received LIN frames. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 423 Figure 23-2. LINFlex block diagram 23.4 Fractional baud rate generation The baud rates for the receiver and transmitter are both set to the same value as programmed in the Mantissa (LINIBRR) and Fraction (LINFBRR) registers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 424 / Desired / Desired LINIBRR LINFBRR baud rate LINIBRR LINFBRR baud rate 2400 2399.97 1666 –0.001 2399.88 –0.005 9600 9599.52 –0.005 9598.08 –0.02 10417 10416.7 –0.003 10416.7 –0.003 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 425 LINFlex is in Sleep mode to reduce power consumption. The software instructs LINFlex to enter Initialization mode or Sleep mode by setting the INIT bit or SLEEP bit in the LINCR1. RESET SLEEP INITIALIZATION NORMAL Figure 23-3. LINFlex operating modes MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 426 Loop Back mode LINFlex can be put in Loop Back mode by setting the LBKM bit in the LINCR. In Loop Back mode, the LINFlex treats its own transmitted messages as received messages. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 427 23.7 Memory map and registers description 23.7.1 Memory map Chapter 3, Memory Map, of this reference manual for the base addresses for the LINFlex modules. Table 23-2 shows the LINFlex memory map. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 428 452 0x0078 Identifier filter control register 11 (IFCR11) on page 452 0x007C Identifier filter control register 12 (IFCR12) on page 452 0x0080 Identifier filter control register 13 (IFCR13) on page 452 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 429 LASE LIN Slave Automatic Resynchronization Enable 0 Automatic resynchronization disable. 1 Automatic resynchronization enable. Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 430 INIT Initialization Request The software sets this bit to switch hardware into Initialization mode. If the SLEEP bit is reset, LINFlex enters Normal mode when clearing the INIT bit (see Table 23-6). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 431 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit Table 23-6. Operating mode selection SLEEP INIT Operating mode Sleep (reset value) Initialization Normal MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 432 0 No interrupt on LIN state change. 1 Interrupt generated on LIN state change. This interrupt can be used for debugging purposes. It has no status flag but is reset when writing 1111 into LINS[0:3] in the LINSR. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 433 1 Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR is set. 23.7.1.3 LIN status register (LINSR) Offset: 0x0008 Access: User read/write Reset LINS RBSY RPS WUF DBFF DBEF DRF DTF HRF Reset Figure 23-8. LIN status register (LINSR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 434 0 Receiver is idle 1 Reception ongoing Note: In Slave mode, after header reception, if BIDR[DIR] = 0 and reception starts then this bit is set. In this case, user cannot program LINCR2[DTRQ] = 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 435 Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say: • All filters are inactive and BF bit in LINCR1 is set • No match in any filter and BF bit in LINCR1 is set • TX filter match MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 436 This bit is set by hardware and indicates that a Identifier Parity error occurred. Note: Header interrupt is triggered when SFEF or BDEF or IDPEF bit is set and HEIE bit in LINIER is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 437 UART bit is set. RDFL[0:1] = Receive buffer size – 1. 00 Receive buffer size = 1. 01 Receive buffer size = 2. 10 Receive buffer size = 3. 11 Receive buffer size = 4. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 438 UART mode status register (UARTSR) Offset: 0x0014 Access: User read/write Reset R SZF OCF PE3 PE0 RMB FEF BOF RPS WUF DRF DTF W w1c Reset Figure 23-11. UART mode status register (UARTSR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 439 LINRX pin in Sleep mode. This bit must be cleared by software. It is reset by hardware in Initialization mode. An interrupt i generated if WUIE bit in LINIER is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 440 Idle on Timeout 0 LIN state machine not reset to Idle on timeout event. 1 LIN state machine reset to Idle on timeout event. This bit can be set/cleared in Initialization mode only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 441 These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR. Output compare 1 value These bits contain the value to be compared to the value of bits CNT[0:7] in LINTCSR. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 442 This field can be written only in Slave mode. 23.7.1.10 LIN fractional baud rate register (LINFBRR) Offset: 0x0024 Access: User read/write Reset DIV_F Reset Figure 23-15. LIN fractional baud rate register (LINFBRR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 443 This field defines the LINFlex divider (LFDIV) mantissa value (see Table 23-17). This field can be written in Initialization mode only. Table 23-17. Integer baud rate selection DIV_M[0:12] Mantissa 0x0000 LIN clock disabled 0x0001 0x1FFE 8190 ox1FFF 8191 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 444 Field Description IOBE Idle on Bit Error 0 Bit error does not reset LIN state machine. 1 Bit error reset LIN state machine. This bit can be set/cleared in Initialization mode only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 445 Cleared by hardware when the request has been completed or aborted. This bit has no effect in UART mode. 23.7.1.14 Buffer identifier register (BIDR) Offset: 0x0034 Access: User read/write Reset DIR CCS Reset Figure 23-19. Buffer identifier register (BIDR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 446 Figure 23-20. Buffer data register LSB (BDRL) Table 23-21. BDRL field descriptions Field Description DATA3 Data Byte 3 Data byte 3 of the data field. DATA2 Data Byte 2 Data byte 2 of the data field. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 447 Data Byte 6 Data byte 6 of the data field. DATA5 Data Byte 5 Data byte 5 of the data field. DATA4 Data Byte 4 Data byte 4 of the data field. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 448 Filters 8 and 9 are activated. FACT[5] Filters 10 and 11 are deactivated. Filters 10 and 11 are activated. FACT[6] Filters 12 and 13 are deactivated. Filters 12 and 13 are activated. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 449 SRAM (see Section 23.8.2.2, Slave mode for more details). When no filter matches, IFMI[0:4] = 0. When Filter n is matching, IFMI[0:4] = n + 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 450 Filters 10 and 11 are in mask mode (filter 11 is the mask for the filter 10). IFM[6] Filters 12 and 13 are in identifier list mode. Filters 12 and 13 are in mask mode (filter 13 is the mask for the filter 12). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 451 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data fields only. This is compatible with LIN specification 1.3 and earlier. Identifier Identifier part of the identifier field without the identifier parity. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 452 0 Enhanced Checksum covering Identifier and Data fields. This is compatible with LIN specification 2.0 and higher. 1 Classic Checksum covering Data field only. This is compatible with LIN specification 1.3 and earlier. Identifier Identifier part of the identifier field without the identifier parity MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 453 Figure 23-28. UART mode 9-bit data frame 23.8.1.1 Buffer in UART mode The 8-byte buffer is divided into two parts: one for receiver and one for transmitter, as shown in Table 23-30. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 454 In this case the latest message is always available to the application. • If the buffer lock function is enabled (LINCR1[RBLM] = 1), the most recent message is discarded and the previous message is available in the buffer. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 455 It is possible to handle frames with a Response size larger than 8 bytes of data (extended frames). If the data field length in the BIDR is configured with a value higher than 8 data bytes, the LINSR[DBEF] bit is MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 456 An interrupt is generated if LINIER[FEIE] = 1. During reception, a Checksum Error leads LINFlex to discard the received frame. LINFlex returns to idle state. An interrupt is generated if LINIER[CEIE] = 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 457 If LINFlex cannot provide enough TX identifier filters to handle all identifiers the software has to transmit data for, then a filter can be configured in mask mode (see Section 23.8.2.3, Slave mode with identifier filtering) in order to manage several identifiers with one filter only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 458 In case of Bit Error detection during transmission, LINFlex stops the transmission of the frame after the corrupted bit. LINFlex returns to idle state and an interrupt is generated if the BEIE bit in the LINIER is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 459 To fulfill this requirement, the LINFlex controller provides configurable filters in order to request software intervention only if needed. This hardware filtering saves CPU resources that would otherwise be needed by software for filtering. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 460 If at least one active filter is configured as TX, all received identifiers matching this filter generate a TX interrupt. If at least one active filter is configured as RX, all received identifiers matching this filter generate an RX interrupt. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 461 This mode is similar to Slave mode as described in Section 23.8.2.2, Slave mode, with the addition of automatic resynchronization enabled by the LASE bit. In this mode LINFlex adjusts the fractional baud rate generator after each Synch Field reception. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 462 If 14.06% < D1 < 14.84%, LHE can be either set or reset depending on the dephasing between the signal on LINFlex_RX pin the f clock. periph_set_1_clk The second check is based on a measurement of time between each falling edge of the Synch Field: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 463 = CNT + RTO × 9 (response timeout value for an Response Response 8-byte frame)). On the first response byte is received, OC1 and OC2 are automatically updated to check T Response according to RTO (tolerance) and DFL. Frame MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 464 Setting LINTCSR[LTOM] = 1 enables the output compare mode. This mode allows the user to fully customize the use of the counter. OC1 and OC2 output compare values can be updated in the LINTOCR by software. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 465 In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector is RXI or TXI depending on the value of identifier received. For debug and validation purposes MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 466 Chapter 23 LIN Controller (LINFlex) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 467 The LINFlexD controller can operate in several modes, each of which has a distinct set of features. These distinct features are described in the following sections. In addition, the LINFlexD controller has several features common to all modes: • Fractional baud rate generator MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 468 UART mode features • Full-duplex communication • Selectable frame size: — 8-bit frame — 9-bit frame — 16-bit frame — 17-bit frame • Selectable parity: — Even — Odd — 0 — 1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 469 Recessive: logical high level (1) 24.3.2 LIN frames A frame consists of a header provided by the master task and a response provided by the slave task, as shown in Figure 24-3. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 470 Delimiter Figure 24-4. Break field 24.3.3.2 Sync The sync pattern is a byte consisting of alternating dominant and recessive bits as shown in Figure 24-5. It forms a data value of 0x55. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 471 • P1 = not(ID1 xor ID3 xor ID4 xor ID5) Start Stop Figure 24-7. Identifier 24.3.4.3 Checksum The checksum contains the inverted 8-bit sum (with carry) over one of two possible groups: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 472 Summary of operating modes The LINFlexD controller has three operating modes: • Normal • Initialization • Sleep After a hardware reset, the LINFlexD controller is in Sleep mode to reduce power consumption. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 473 In Initialization mode, all message transfers to and from the LIN bus are stopped and the LIN bus output (LINTX) is recessive. Entering Initialization mode does not change any of the configuration registers. To initialize the LINFlexD controller, the software must: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 474 To transmit a header with LINFlexD the application must set up the identifier and the data field length, and configure the message (direction and checksum type) in the BIDR register before requesting the header transmission by setting LINCR2[HTRQ]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 475 After the message buffer is full, the next valid message reception causes an overrun and a message is lost. The LINFlexD controller sets LINSR[BOF] to signal the overrun condition. Which message is lost depends on the configuration of the RX message buffer: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 476 Read the received ID in the BIDR register • Specify the data field length using the BIDR[DFL] field before the reception of the stop bit of the first byte of data field MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 477 If encountered during reception: stop bit of the currently received character • Discards the current frame (sync field, identifier, or data field) • Generates an interrupt if LINIER[FEIE] is • Returns immediately to idle state MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 478 If the message does not target the node, it must be discarded without software intervention. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 479 Identifier filter configuration Identifier filter submode Identifier list submode Identifier IFCR IFM = 0 IFCR Identifier 2n+1 Mask submode Identifier IFCR IFM = 1 IFCR Mask 2n+1 Figure 24-9. Filter configuration—register organization MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 480 • RX interrupt on IDs (b > 0) matching the filters • TX interrupt on all other IDs if BF bit is set, no TX interrupt if BF bit is reset MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 481 Figure 24-11. LIN sync field measurement LFDIV is an unsigned fixed point number. The mantissa is coded on 20 bits in the LINIBRR register and the fraction is coded on 4 bits in the LINFBRR register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 482 Loop Back mode LINFlexD can be put in Loop Back mode by setting LINCR1[LBKM]. In Loop Back mode, the LINFlexD treats its own transmitted messages as received messages. This is illustrated in Figure 24-12. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 483 0, or 1) can be selected by the UARTCR[PC] field. An even parity is set if the modulo-2 sum of the 7 data bits is 1. An odd parity is cleared in this case. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 484 24-17. The 17th bit is the parity bit. Parity (even, odd, 0, or 1) can be selected by the UARTCR[PC] field. Parity 0 forces a zero logical value. Parity 1 forces a high logical value. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 485 The buffer can be configured in FIFO mode (mandatory when DMA Tx is enabled) by setting UARTCR[TFBM]. The access to the BDRL register is shown in Table 24-6. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 486 If the UARTCR[RXEN] field is cleared during a reception, the current reception is completed, but no further reception can be invoked until UARTCR[RXEN] is set again. The buffer can be configured in FIFO mode (required when DMA Rx is enabled) by setting UARTCR[RFBM]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 487 The reception will hang. In this case, the software must number of bytes received, but the actual number of bytes monitor the UARTSR[TO] field, and move to IDLE state received is smaller. by setting LINCR1[SLEEP]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 488 INIT Reset These fields are writable only in Initialization mode (LINCR1[INIT] = 1). Resets to 0 in Slave mode and to 1 in Master mode Figure 24-18. LIN control register 1 (LINCR1) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 489 Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode Master Mode Enable 0: Slave mode enable 1: Master mode enable Note: This bit can be written in Initialization mode only. It is read-only in Normal or Sleep mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 490 Hardware calculated Table 24-11. LIN master break length selection Length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 491 Field Description SZIE Stuck at Zero Interrupt Enable 0: No interrupt when SZF bit in LINESR or UARTSR is set 1: Interrupt generated when SZF bit in LINESR or UARTSR is set MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 492 Header Received Interrupt Enable 0: No interrupt when a valid LIN header has been received 1: Interrupt generated when a valid LIN header has been received, that is, HRF bit in LINSR register is set MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 493 Chapter 24 LIN Controller (LINFlexD) 24.10.3 LIN status register (LINSR) Offset: 0x08 Access: User read/write Reset LINS RPS WUF DRF DTF HRF Reset Figure 24-20. LIN status register (LINSR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 494 Note: In Slave mode, after header reception, if DIR bit in BIDR is reset and reception starts then this bit is set. In this case, user cannot set DTRQ bit in LINCR2. LIN receive pin state This bit reflects the current status of LINRX pin for diagnostic purposes. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 495 Note: If filters are enabled, this bit is set only when identifier software filtering is required, that is to say: • all filters are inactive and BF bit in LINCR1 is set • no match in any filter and BF bit in LINCR1 is set • TX filter match MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 496 This bit is set by hardware and indicates that a Synch Field error occurred (inconsistent Synch Field). BDEF Break Delimiter Error Flag This bit is set by hardware and indicates that the received Break Delimiter is too short (less than one bit time). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 497 Reset These fields are read/write in UART buffer mode and read-only in other modes. These fields are writable only in Initialization mode (LINCR1[INIT] = 1). Figure 24-22. UART mode control register (UARTCR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 498 Rx FIFO/buffer mode 0 Rx buffer mode enabled 1 Rx FIFO mode enabled (mandatory in DMA Rx mode) This field can be programmed in initialization mode only when the UART bit is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 499 This field can be programmed in Initialization mode only when the UART bit is set. UART UART mode enable 0: LIN mode 1: UART mode This field can be programmed in Initialization mode only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 500 Parity Error Flag Rx0 This bit indicates if there is a parity error in the corresponding received byte (Rx0). No interrupt is generated if this error occurs. 0: No parity error 1: Parity error MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 501 • In UART FIFO mode (TFBM = 1), it indicates that the Tx FIFO is full. This field is a read-only field used internally by the DMA Tx interface. Noise Flag This bit is set by hardware when noise is detected on a received character. This bit is cleared by software. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 502 TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in LIN timeout mode, then hardware takes control of TOCE bit. Counter Value These bits indicate the LIN Timeout counter value. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 503 Output compare 2 value These bits contain the value to be compared to the value of LINTCSR[CNT]. Output compare 1 value These bits contain the value to be compared to the value of LINTCSR[CNT]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 504 This register contains the header timeout duration (in bit time). This value does not include the first 11 dominant bits of the Break. The reset value depends on which mode LINFlexD is in. HTO can be written only for Slave mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 505 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This field is writable only in Initialization mode (LINCR1[INIT] = 1). Figure 24-28. LIN integer baud rate register (LINIBRR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 506 Figure 24-29. LIN checksum field register (LINCFR) Table 24-24. LINCFR field descriptions Field Description Checksum bits When LINCR1[CCD] is cleared, these bits are read-only. When LINCR1[CCD] is set, these bits are read/write. See Table 24-10. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 507 Cleared by hardware when the request has been completed or aborted or on an error condition. In Master mode, this bit is set by hardware when DIR bit in BIDR is set and header transmission is completed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 508 DFL[0:2] and DFL[0:5] . DFL[3:5] are provided to manage extended frames. Direction This bit controls the direction of the data field. 0: LINFlexD receives the data and copy them in the BDR registers. 1: LINFlexD transmits the data from the BDR registers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 509 Data Byte 2 Data byte 2 of the data field DATA1 Data Byte 1 Data byte 1 of the data field DATA0 Data Byte 0 Data byte 0 of the data field MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 510 Data Byte 6 Data byte 6 of the data field DATA5 Data Byte 5 Data byte 5 of the data field DATA4 Data Byte 4 Data byte 4 of the data field MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 511 Filters 4 and 5 are activated. FACT[3] Filters 6 and 7 are deactivated. Filters 6 and 7 are activated. FACT[4] Filters 8 and 9 are deactivated. Filters 8 and 9 are activated. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 512 This register contains the index corresponding to the received ID. It can be used to directly write or read the data in RAM (refer to Section 24.7.2, Slave mode, for more details). When no filter matches, IFMI = 0. When Filter n is matching, IFMI = n + 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 513 If a = (number of filters) / 2, and n = 0 to (a – 1), then IFCR[2n] acts as a filter and IFCR[2n + 1] acts as the mask for IFCR[2n]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 514 Identifier part of the identifier field without the identifier parity. 24.10.21 Global control register (GCR) This register can be programmed only in Initialization mode. The configuration specified in this register applies in both LIN and UART modes. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 515 This field controls the number of stop bits in transmitted data in both UART and LIN modes. The stop bit is configured for all the fields (delimiter, sync, ID, checksum, and payload). 0 One stop bit 1 Two stop bits MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 516 The timeout counter: • Starts at 0 and counts upward • Is clocked with the baud rate clock prescaled by a hard-wired scaling factor of 16 • Is automatically enabled when UARTCR[RXEN] = 1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 517 When CTO matches the value of UARTPTO[PTO], UARTSR[TO] is set. 24.10.24 DMA Tx enable register (DMATXE) This register enables the DMA Tx interface. Offset: 0x98 Access: User read/write Reset Reset Figure 24-41. DMA Tx enable register (DMATXE) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 518 The LINFlexD controller interacts with an enhanced direct memory access (eDMA) controller; see the description of that controller for details on its operation and the transfer control descriptors (TCDs) referenced in this section. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 519 Table 24-40. Register settings (master node, TX mode) LIN frame LINCR2 BIDR Master to Slave DDRQ=1 DFL = payload size DTRQ=0 ID = address HTRQ=0 CCS = checksum DIR = 1 (TX) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 520 The concept FSM to control the DMA TX interface is shown in Figure 24-44. The DMA TX FSM will move to IDLE state immediately at next clock edge if DMATXE[0] = 0. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 521 Figure 24-44. FSM to control the DMA TX interface (master node) The TCD settings (word transfer) are shown in Table 24-41. All other TCD fields are equal to 0. TCD settings based on half-word or byte transfers are allowed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 522 1 DMA RX channel (TCD single and/or linked chain) Figure 24-45. TCD chain memory map (master node, RX mode) The TCD chain of the DMA Rx channel on a master node supports Slave-to-Master reception of the data field. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 523 Figure 24-46. FSM to control the DMA RX interface (master node) The TCD settings (word transfer) are shown in Table 24-42. All other TCD fields are equal to 0. TCD settings based on half-word or byte transfer are allowed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 524 BDRL + BDRM BDRL + BDRM Extended TCD (n+2) (4/8 bytes) (4/8 bytes) Frame (n+2) 1 DMA TX channel/filter (TCD single and/or linked chain) Figure 24-47. TCD chain memory map (slave node, TX mode) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 525 The concept FSM to control the DMA Tx interface is shown in Figure 24-48. DMA TX FSM will move to idle state if DMATXE[x] = 0, where x = IFMI – 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 526 Figure 24-48. FSM to control the DMA TX interface (slave node) The TCD settings (word transfer) are shown in Table 24-44. All other TCD fields are equal to 0. TCD settings based on half-word or byte transfer are allowed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 527 BDRL + BDRM BDRL + BDRM TCD (n+2) Frame (n+2) (4/8 bytes) (4/8 bytes) 1 DMA RX channel/filter (TCD single and/or linked chain) Figure 24-49. TCD chain memory map (slave node, RX mode) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 528 The concept FSM to control the DMA Rx interface is shown in Figure 24-50. DMA RX FSM will move to idle state if DMARXE[x] = 0 where x = IFMI – 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 529 Single iteration for the major loop NBYTES[31:0] [4] + 4/8 = N Data buffer is stuffed with dummy bytes if the length is not word aligned. BIDR + BDRL + BDRM SADDR[31:0] BDRL address MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 530 Adsorb the latency, following a DMA request (due to the DMA arbitration), to move data from the RAM to the FIFO • Use low priority DMA channels • Support the UART baud rate (2 Mb/s) without underrun events The Tx FIFO size is: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 531 The TCD settings (typical case) are shown in Table 24-47. All other TCD fields = 0. The minor loop transfers a single byte/half-word as soon a free entry is available in the Tx FIFO. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 532 (M bytes) Buffer (n+1) TCD (n+1) BDRM BDRM (2 half-words FIFO mode) (M half-words) 1 DMA RX channel (TCD single and/or linked chain) Figure 24-53. TCD chain memory map (UART node, RX mode) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 533 FIFO not empty (RX) status signals. The concept FSM to control the DMA Rx interface is shown in Figure 24-54. DMA Rx FSM will move to idle state if DMARXE[0] = 0. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 534 The TCD settings (typical case) are shown in Table 24-48. All other TCD fields = 0. The minor loop transfers a single byte/half-word as soon an entry is available in the Rx FIFO. A new software reset bit is MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 535 The DMA capability does not provide support for the error management. Error management means checking status bits, handling IRQs, and potentially canceling DMA transfers. • The DMA programming model must be coherent with the TCD setting defined in this document. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 536 (DFL = 7) is always assumed. 24.12.1.1.2 LIN Slave mode Field RTO in the LINTOCR can be used to tune response timeout and frame timeout values. Header timeout value is fixed to HTO. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 537 OC1 and OC2 output compare values can be updated in the LINTOCR by software. 24.12.2 Interrupts Table 24-49. LINFlexD interrupt control Interrupt event Event flag bit Enable control bit Interrupt vector Header Received interrupt HRIE Data Transmitted interrupt DTIE MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 538 In Slave mode, if at least one filter is configured as TX and enabled, header received interrupt vector is RXI or TXI depending on the value of identifier received. For debug and validation purposes. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 539 LFDIV is an unsigned fixed point number. The 20-bit mantissa is coded in the LINIBRR register and the fraction is coded in the LINFBRR register. The following examples show how to derive LFDIV from LINIBRR and LINFBRR register values: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 540 This section describes the various configurations in which the LINFlexD can be used. 24.13.1 Master node Header Data TX Checksum TX DIR = 1 Configure ID DTF set DFL, Data buffer TXI Interrupt Set HTRQ Figure 24-57. Programming consideration: master node, transmitter MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 541 24.13.2 Slave node Header Data TX Checksum TX DTF set HRF set Configure CCS, DIR, DFL, TX Interrupt RX Interrupt Data Buffers Set DTRQ Figure 24-61. Programming consideration: slave node, transmitter, no filters MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 542 Note: This configuration can be used in case the slave never receives data (for example, as with a sensor). Figure 24-65. Programming consideration: slave node, at least one TX filter, BF is reset, ID matches filter MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 543 All TX IDs are managed by filters b) The number of other filters is not enough to manage all reception IDs Figure 24-68. Programming consideration: slave node, TX filter, BF is set MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 544 The number of filters is not enough b) Filters are used for most frequently used IDs to reduce CPU usage Figure 24-70. Programming consideration: slave node, TX filter, RX filter, BF is set MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 545 Figure 24-72. Programming consideration: response timeout frame_max Header Data receive/transmit transmit/receive OCF is set ERR interrupt Figure 24-73. Programming consideration: frame timeout header_max Header receive Break OCF is set ERR interrupt Figure 24-74. Programming consideration: header timeout MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 546 Chapter 24 LIN Controller (LINFlexD) 24.13.5 UART mode Data receive/transmit DTF/DRF is set Set TXen/RXen Transmit/receive interrupt Write buffer for transmit Figure 24-75. Programming consideration: UART mode MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 547 Chapter 24 LIN Controller (LINFlexD) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 548 Chapter 24 LIN Controller (LINFlexD) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 549 Message Buffers (MB) and another one for storing Rx Individual Mask registers. Support for as many as 64 Message Buffers is provided. The functions of the sub-modules are described in subsequent sections. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 550 ID matching algorithms. The Bus Interface Unit (BIU) submodule controls the access to and from the internal interface bus in order to MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 551 Low power modes, with programmable wake up on bus activity 25.2.3 Modes of operation The FlexCAN module has four functional modes: Normal mode (User and Supervisor), Freeze mode, Listen-Only mode, and Loop-Back mode. There is also a low-power mode (Disable mode). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 552 Table 25-1. FlexCAN Signals Signal Name Direction Description CAN Rx Input CAN Receive Pin CAN Tx Output CAN Transmit Pin The actual MCU pins may have different names. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 553 When it is configured with 32 MBs, the memory sizes are 544 and 128 bytes, so the address ranges 0x0280–0x047F and 0x0900–0x097F are considered reserved space. Furthermore, if the BCC bit in MCR is negated, then the whole Rx Individual Mask registers address range (0x0880–0x097F) is considered reserved space. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 554 Standard/Extended Message Buffer (MB0) memory map, using 16 bytes total (0x80 0x8F space). – Table 25-3. Message Buffer MB0 memory mapping Address Offset MB Field 0x80 Control and Status (C/S) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 555 0 Indicates the current MB has a Data Frame to be transmitted. 1 Indicates the current MB has a Remote Frame to be transmitted. Note: Do not configure the last Message Buffer to be the RTR frame. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 556 If the MB is FULL and a new frame is overwritten to this MB before the CPU had time to read it, the code is automatically updated to OVERRUN. See Section 25.5.6, Matching process, for details about overrun behavior. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 557 MBM as a result of match to a remote request frame. The data frame will be transmitted unconditionally once and then the code will automatically return to 1010. The CPU can also write this code with the same effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 558 ID Table 2 0xEC ID Table 3 0xF0 ID Table 4 0xF4 ID Table 5 0xF8 ID Table 6 0xFC ID Table 7 = Unimplemented or Reserved Figure 25-3. Rx FIFO structure MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 559 This register defines global system configurations, such as the module operation mode (e.g., low power) and maximum message buffer configuration. This register can be accessed at any time, however some fields must be changed only during Freeze Mode. Find more information in the fields descriptions ahead. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 560 (0x80–0xFF) is used by the FIFO engine. See Section 25.4.3, Rx FIFO structure, and Section 25.5.8, Rx FIFO, for more information. This bit must be written in Freeze mode only. 0 FIFO not enabled 1 FIFO enabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 561 0 Affected registers are in Unrestricted memory space 1 Affected registers are in Supervisor memory space. Any access without supervisor permission behaves as though the access was done to an unimplemented register location MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 562 This feature guarantees a safe procedure for aborting a pending transmission, so that no frame is sent in the CAN bus without notification. This bit must be written in Freeze mode only. 0 Abort disabled 1 Abort enabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 563 Most of the fields in this register should only be changed while the module is in Disable Mode or in Freeze Mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK, and BOFF_REC bits, which can be accessed at any time. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 564 This bit provides a mask for the Bus Off Interrupt. 0 Bus Off interrupt disabled 1 Bus Off interrupt enabled ERR_MSK Error Mask This bit provides a mask for the Error Interrupt. 0 Error interrupt disabled 1 Error interrupt enabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 565 If BOFF_REC was negated when the module entered Bus Off, asserting it during Bus Off will not be effective for the current Bus Off recovery. 0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B 1 Automatic recovering from Bus Off state disabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 566 If desired, software can poll the register to discover when the data was actually written. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 567 The mask bits one-to-one correspondence occurs with the filters bits, not with the incoming message ID bits. This leads the RXGMASK to affect Rx MB and Rx FIFO filtering in different ways. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 568 MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16 RESET: MI15 MI14 MI13 MI12 MI11 MI10 MI9 RESET: Figure 25-8. Rx Global Mask (RXGMASK) register MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 569 25.4.4.7 Error Counter Register (ECR) This register has two 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter (TX_ERR_COUNTER field) and Receive Error Counter (RX_ERR_COUNTER field). The rules MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 570 At the next successful message reception, the counter is set to a value between 119 and 127 to resume to Error Active state. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 571 Most bits in this register are read-only, except TWRN_INT, RWRN_INT, BOFF_INT, and ERR_INT, which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). See Section 25.5.11, Interrupts, for more details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 572 This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 0 No such occurrence 1 At least one bit sent as dominant is received as recessive MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 573 Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect. 0 No such occurrence 1 FlexCAN module entered Bus Off state MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 574 0 The corresponding buffer Interrupt is disabled 1 The corresponding buffer Interrupt is enabled Note: Setting or clearing a bit in the IMASK2 register can assert or negate an interrupt request, if the corresponding IFLAG2 bit is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 575 When the AEN bit in the MCR is set (Abort enabled), while the IFLAG2 bit is set for a MB configured as Tx, the writing access done by CPU into the corresponding MB will be blocked. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 576 When the MCR[FEN] bit is set (FIFO enabled), the function of the 8 least significant interrupt flags (BUF7I–BUF0I) is changed to support the FIFO operation. BUF7I, BUF6I, and BUF5I indicate operating conditions of the FIFO, while BUF4I to BUF0I are not used. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 577 Message Buffer, providing ID masking capability on a per Message Buffer basis. When the FIFO is enabled (FEN bit in MCR is set), the first 8 Mask MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 578 MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides the prioritization of MBs to be transmitted based on the message ID (optionally augmented by 3 local priority bits) or the MB ordering. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 579 Interrupt Mask register bit. The new Code field after transmission depends on the code that was used to activate the MB in step four (see Table 25-5 Table 25-6 Section 25.4.2, Message Buffer MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 580 1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 581 MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may be lost. In summary: never do polling by reading directly the C/S word of the MBs. Instead, read the IFLAG registers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 582 ID. Let us say that these MBs are the second and the fifth in the array. When the first message arrives, the matching algorithm will find the first match in MB number 2. The code MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 583 MB is not deactivated, but the abort request is captured and kept pending until one of the following conditions is satisfied: • The module loses the bus arbitration MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 584 MBs have a matching ID to a received frame, and the user deactivated the first matching MB after FlexCAN has scanned the second. The received frame will be lost even if the second matching MB was free to receive. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 585 SMB will not be transferred anymore to the MB. 1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was EMPTY. This behavior will be honored when the BCC bit is negated. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 586 MB as Transmit with the RTR bit set to 1. After the Remote Request frame is transmitted successfully, the MB becomes a Receive Message Buffer, with the same ID as before. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 587 (Oscillator Clock) or to the Peripheral Clock (generally from a PLL). In order to guarantee reliable operation, the clock source should be selected while the module is in Disable Mode (bit MDIS set in MCR). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 588 Þ Time Þ Quanta For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 589 It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information Processing Time) of 2, which is the value implemented in the FlexCAN module. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 590 This mode is entered by asserting the HALT bit in MCR or when the MCU is put into Debug mode. In both cases it is also necessary that the FRZ bit is asserted in MCR and the module is not in a low-power mode MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 591 The module can generate as many as 70 interrupt sources (64 interrupts due to message buffers and 6 interrupts due to ORed interrupts from MBs, Bus Off, Error, Tx Warning, Rx Warning, and Wake Up). The number of actual sources depends on the configured number of Message Buffers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 592 0x0060 to 0x007F is reserved (for SMB usage), and the space from 0x0080 to 0x008F is used by the one MB. This leaves us with the available space from 0x0090 to 0x047F. The available memory in the Mask Registers space would be from 0x0884 to 0x097F. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 593 — Enable the local priority feature by setting the LPRIO_EN bit • Initialize CTRL — Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW — Determine the bit rate by programming the PRESDIV field MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 594 MAXMB field in MCR. For 16 MB configuration, MAXMB can be any number between 0–15. For 32 MB configuration, MAXMB can be any number between 0–31. For 64 MB configuration, MAXMB can be any number between 0–63. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 595 MCU and an external peripheral device. The MPC5606BK has six identical DSPI modules (DSPI_0 – DSPI_5). The “x” appended to signal names signifies the module to which the signal applies. Thus CS0_x specifies that the CS0 signal applies to DSPI module 0, 1, etc.
Page 596 Deglitching support for as many as 32 peripheral chip selects with external demultiplexer • Two DMA conditions for SPI queues residing in RAM or flash — TX FIFO is not full (TFFF) — RX FIFO is not empty (RFDF) • Six interrupt conditions: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 597 DSPI is stopped while in module disable mode. The DSPI enters the module disable mode when the MDIS bit in DSPIx_MCR is set. For more information, see Section 26.6.1.3, Module Disable mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 598 When the pin is used for DSPI master mode as a chip select output, set the OBE bit. When the pin is used in DSPI slave mode as a slave select input, set the IBE bit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 599 SCK_x is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave mode, SCK_x is an input from an external bus master. 26.5 Memory map and register description 26.5.1 Memory map Table 26-2 shows the DSPI memory map. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 600 MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT and MDIS bits in the DSPIx_MCR are the only bit values software can change while the DSPI is running. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 601 0 Continuous SCK disabled Note: 1Continuous SCK enabled DCONF DSPI configuration The following table lists the DCONF values for the various configurations. DCONF Configuration Invalid value Invalid value Invalid value MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 602 Enables and disables the TX FIFO. When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. See Section 26.6.3.3, FIFO disable operation details. 0 TX FIFO is enabled 1 TX FIFO is disabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 603 The DSPIx_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter is intended to assist in queue management. The user must not write to the DSPIx_TCR while the DSPI is running. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 604 • MSB or LSB first DSPIx_CTARs support compatibility with the QSPI module in the MPC5606BK family of MCUs. At the initiation of an SPI transfer, control logic selects the DSPIx_CTAR that contains the transfer’s attributes. Do not write to the DSPIx_CTARs while the DSPI is running.
Page 605 0 Data is captured on the leading edge of SCK and changed on the following edge 1 Data is changed on the leading edge of SCK and captured on the following edge MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 606 PCS at the beginning of the next frame. The PDT field is only used in Master Mode. The table below lists the prescaler values. See the DT[0:3] field description for details on how to compute the delay after transfer. Delay after transfer prescaler value MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 607 Communications Clock operation the DT value is fixed to one TSCK. The Delay after Transfer is a multiple of the system clock period and it is computed according to the following equation:   Eqn. 26-3 ---------- - Section 26.6.4.4, Delay after transfer (tDT), for more details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 608 57/43 Table 26-7. DSPI transfer frame size FMSZ Frame size FMSZ Frame size 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 609 Delay after transfer scaler Delay after transfer scaler value value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768 0111 1111 65536 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 610 57/43 Table 26-13. DSPI transfer frame size FMSZ Frame size FMSZ Frame size 0000 Reserved 1000 0001 Reserved 1001 0010 Reserved 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 611 Delay after transfer scaler Delay after transfer scaler value value 0000 1000 0001 1001 1024 0010 1010 2048 0011 1011 4096 0100 1100 8192 0101 1101 16384 0110 1110 32768 0111 1111 65536 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 612 Module Disable mode due to the use of power saving mechanisms. Offset: 0x2C Access: R/W TFUF TFFF W w1c Reset TXCTR TXNXTPTR RXCTR POPNXTPTR Reset Figure 26-6. DSPI Status Register (DSPIx_SR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 613 Indicates that an overflow condition in the RX FIFO has occurred. The bit is set when the RX FIFO and shift register are full and a transfer is initiated. 0 RX FIFO overflow has not occurred 1 RX FIFO overflow has occurred MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 614 • It selects the type of request to generate. See the bit descriptions for the type of requests that are supported. Do not write to the DSPIx_RSER while the DSPI is running. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 615 DSPIx_SR is set, and the TFFF_RE bit in the DSPIx_RSER is set, this bit selects between generating an interrupt request or a DMA request. 0 Interrupt request is selected 1 DMA request is selected MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 616 Write accesses of 8 or 16 bits to the DSPIx_PUSHR transfers 32 bits to the TX FIFO. NOTE TXDATA is used in master and slave modes. Offset:0x34 Access: Read/write CTAS Reset TXDATA Reset Figure 26-8. DSPI PUSH TX FIFO Register (DSPIx_PUSHR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 617 SPI_TCNT field in the DSPIx_TCR. The SPI_TCNT field is cleared before transmission of the current SPI frame begins. 0 Do not clear SPI_TCNT field in the DSPIx_TCR 1 Clear SPI_TCNT field in the DSPIx_TCR Note: Use in SPI master mode only. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 618 Figure 26-9. DSPI POP RX FIFO Register (DSPIx_POPR) Table 26-21. DSPIx_POPR field descriptions Field Description RXDATA Received data The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer (POPNXTPTR). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 619 RX FIFO. The DSPIx_RXFR registers are read-only. Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is DSPIx_RXFR0–DSPIx_RXFR3 are used. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 620 At the end of a transfer, the TCF bit in the DSPIx_SR is set to indicate a completed transfer. Figure 26-12 illustrates how master and slave data is exchanged. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 621 FIFO entry. The CTAS field in the SPI command selects which of the DSPIx_CTARs are used to set the transfer attributes. Transfer attribute control is on a frame by frame basis. Section 26.6.3, Serial peripheral interface (SPI) configuration for more details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 622 RESET RUNNING TXRXS = 1 Power-on-Reset STOPPED TXRXS = 0 Figure 26-13. DSPI start and stop state diagram The transitions are described in Table 26-24. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 623 The data field in the executing TX FIFO entry is loaded into the shift register and shifted out on the serial out MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 624 The TXNXTPTR field indicates which TX FIFO entry is transmitted during the next transfer. The TXNXTPTR contains the positive offset from DSPIx_TXFR0 in number of 32-bit registers. For example, TXNXTPTR equal to two means that the DSPIx_TXFR2 contains the SPI data and command for the next MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 625 For example, POPNXTPTR equal to two means that the DSPIx_RXFR2 contains the received SPI data that is returned when DSPIx_POPR is read. The POPNXTPTR field is incremented every time the DSPIx_POPR is read. POPNXTPTR rolls over every four frames on the MCU. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 626 BR fields in the DSPIx_CTARs select the frequency of SCK_x using the following formula: f SYS SCK baud rate --------------------------------------------------------- - ¥ -------------------------------------------- PBRPrescalerValue BRScalerValue Table 26-25 shows an example of a computed baud rate. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 627 CSx signal for the next frame. The PDT and DT fields in the DSPIx_CTARn registers select the delay after transfer. Figure 26-16 for an illustration of the delay after transfer. The following formula expresses the PDT/DT/delay after transfer relationship: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 628 PCSSCK Table 26-29. Peripheral chip select strobe assert computation example PCSSCK Prescaler Delay before transfer 0b11 64 MHz 109.4 ns Table 26-30 shows an example of the computed the t delay. PASC MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 629 Section 26.6.5.4, Modified SPI transfer format (MTFE = 1, CPHA = In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames. Section 26.6.5.5, Continuous selection format for details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 630 For the CPHA = 0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial clock edge of the frame (edge 16) of Figure 26-16. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 631 For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of Figure 26-17. For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 632 Figure 26-18 shows the modified transfer format for CPHA = 0. Only the condition where CPOL = 0 is illustrated. The delayed master sample points are indicated with a lighter shaded arrow. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 633 For the modified transfer format to operate correctly, you must thoroughly analyze the SPI link timing budget. Figure 26-19 shows the modified transfer format for CPHA = 1. Only the condition where CPOL = 0 is described. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 634 Master SOUT Master SIN = CS to SCK delay. = After SCK delay. = Delay after transfer (minimum CS negation time). Figure 26-20. Example of non-continuous format (CPHA = 1, CONT = 0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 635 If it is desired to switch polarity between non-continuous DSPI frames, the edge generated by the change in the idle state of the clock occurs one system clock before the assertion of the chip select for the next frame. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 636 SCK format with continuous selection disabled. NOTE When in Continuous SCK mode, always use CTAR0 for the SPI transfer, and clear the TXFIFO using the MCR[CLR_TXF] field before initiating transfer. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 637 DMA requests. Table 26-32 lists the seven conditions. Table 26-32. Interrupt and DMA request conditions Condition Flag Interrupt End of transfer queue has been reached (EOQ) EOQF TX FIFO is not full TFFF MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 638 SPI master. If the TFUF bit is set while the TFUF_RE bit in the DSPIx_RSER is set, an interrupt request is generated. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 639 DSPI return the correct values when read, but writing to them has no affect. Writing to the DSPIx_TCR during module disable mode does not have an effect. Interrupt and DMA request signals cannot be cleared while in the module disable mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 640 PBR and the baud rate scaler BR in the DSPIx_CTARs. The values are calculated at a 64 MHz system frequency. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 641 3.12 kHz 2.23 kHz 4096 3.90 kHz 2.60 kHz 1.56 kHz 1.11 kHz 8192 1.95 kHz 1.31 kHz 781 Hz 558 Hz 16384 979 Hz 653 Hz 390 Hz 279 Hz 32768 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 642 The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer (POPNXTPTR). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 643 The memory address of the last-in entry in the RX FIFO is computed by the following equation: Last-in entry address = RXFIFO base + 4 × [(RXCTR + POPNXTPTR – 1) modulo RXFIFO depth] where: RXFIFO base = base address of receive FIFO MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 644 Chapter 26 Deserial Serial Peripheral Interface (DSPI) RXCTR = receive FIFO counter POPNXTPTR = pop next pointer RX FIFO depth = receive FIFO depth, implementation specific MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 645 ——— Timers ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 646 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 647 This section gives a technical overview of each of the timers as well as detailing the pins that can be used to access the timer peripherals if applicable. Figure 27-1 details the interaction between the timers and the eDMA, INTC, CTU, and ADC. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 648 Chapter 27 Timers Figure 27-1. Interaction between timers and relevant peripherals MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 649 The PWM trigger can then cause the CTU to perform a single ADC conversion, which in turn measures the operating conditions of the LED to ensure it is working within specification. A watchdog feature on MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 650 UC[6] PH[4] UC[22] PE[15] UC[7] PH[5] UC[23] PG[0] UC[8] PH[6] UC[24] PG[1] UC[9] PH[7] UC[25] PF[12] PH[12] UC[10] PH[8] UC[26] PF[13] PH[13] UC[11] PG[2] UC[27] PF[14] PH[14] UC[12] PG[3] UC[28] PI[4] PC[6] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 651 The STM includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 652 0x001C Reserved 0x0020 STM Channel 1 Control Register (STM_CCR1) on page 652 0x0024 STM Channel 1 Interrupt Register (STM_CIR1) on page 653 0x0028 STM Channel 1 Compare Register (STM_CMP1) on page 654 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 653 STM Control Register (STM_CR) The STM Control Register (STM_CR) includes the prescale value, freeze control, and timer enable bits. Offset: 0x000 Access: Read/Write Reset FRZ TEN Reset Figure 27-2. STM Control Register (STM_CR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 654 27.3.3.2.3 STM Channel Control Register (STM_CCRn) The STM Channel Control Register (STM_CCRn) has the enable bit for channel n of the timer. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 655 Figure 27-5. STM Channel Interrupt Register (STM_CIRn) Table 27-7. STM_CIRn field descriptions Field Description Channel Interrupt Flag 0 = No interrupt request. 1 = Interrupt request due to a match on the channel. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 656 The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to the STM_CIRn[CIF] bit has no effect. NOTE STM counter does not advance when the system clock is stopped. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 657 General purpose input/output • Single Action Input Capture • Single Action Output Compare • Input Pulse Width Measurement • Input Period Measurement • Double Action Output Compare • Modulus Counter • Modulus Counter Buffered MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 658 If an unimplemented mode (reserved) is selected, the results are unpredictable such as writing a reserved value to MODE[0:6] in Section 27.4.3.2.8, eMIOS UC Control Register (EMIOSC[n]). 27.4.1.4 Channel implementation Figure 27-7 shows the channel configuration of the eMIOS blocks. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 659 Buffered Output Pulse Width Modulation with Trigger OPWFMB Buffered Output Pulse Width and Frequency Modulation OPWMCB Center Aligned Output PWM Buffered with Dead Time SAIC Single Action Input Capture SAOC Single Action Output Compare MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 660 Disable Channel (EMIOSUCDIS) Register on page 662 0x010–0x01F Reserved — 0x020–0x11F Channel [0] — Channel [7] 0x120–0x21F Channel [8] — Channel [15] 0x220–0x31F Channel [16] — Channel [23] 0x320–0x41F Channel [24] Channel [31] 0x420–0xFFF Reserved MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 661 Puts the eMIOS in low power mode. The MDIS bit is used to stop the clock of the block, except the access to registers EMIOSMCR, EMIOSOUDIS, and EMIOSUCDIS. 1 = Enter low power mode 0 = Clock is running MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 662 The EMIOSGFLAG is a read-only register that groups the flag bits (F[31:0]) from all channels. This organization improves interrupt handling on simpler devices. Each bit relates to one channel. For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS[n] register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 663 27.4.3.2.3 eMIOS Output Update Disable (EMIOSOUDIS) Register Address: eMIOS base address +0x08 Reset OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0 Reset Figure 27-10. eMIOS Output Update Disable (EMIOSOUDIS) Register MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 664 Description CHDISn Enable Channel [n] bit The CHDIS[n] bit is used to disable each of the channels by stopping its respective clock. 1 = Channel [n] disabled 0 = Channel [n] enabled MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 665 Depending on the channel configuration, it may have EMIOSB register or not. This means that, if at least one mode that requires the register is implemented, then the register is present; otherwise it is absent. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 666 Depending on the channel configuration it may have an internal counter or not. It means that if at least one mode that requires the counter is implemented, then the counter is present; otherwise it is absent. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 667 This field selects one of the four output disable input signals, as follows: 00 = Output Disable Input 0 01 = Output Disable Input 1 10 = Output Disable Input 2 11 = Output Disable Input 3 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 668 Bus Select The BSL field is used to select either one of the counter buses or the internal counter to be used by the Unified Channel. Refer to Table 27-20 for details. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 669 Note: If a reserved value is written to mode the results are unpredictable. Table 27-18. UC internal prescaler clock divider UCPRE Divide ratio Table 27-19. UC input filter bits Minimum input pulse width [FLT_CLK periods] 0000 Bypassed 0001 0010 0100 1000 all others Reserved MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 670 Output Pulse Width and Frequency Modulation Buffered 10110b1 Reserved 10111b0 Center Aligned Output Pulse Width Modulation Buffered (with trailing edge dead time) 10111b1 Center Aligned Output Pulse Width Modulation Buffered (with leading edge dead time) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 671 The FLAG bit is set when an input capture or a match event in the comparators occurred. 1 = FLAG set event has occurred 0 = FLAG cleared Note: When DMA bit is set, the FLAG bit can be cleared by the DMA controller or the CTU. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 672 3. Channels of type X and G have the internal counter enabled, so their timebase can be selected by channel's BSL[1:0]=11: eMIOS_A—channels 0 to 8, 16, 23, and 24 eMIOS_B—channels 0, 8, 16, 23, and 24. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 673 Register EMIOSA[n] returns the value of register A2. As soon as the SAIC mode is entered coming out from GPIO mode the channel is ready to capture events. The events are MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 674 In this case, the FLAG bit is not set. When SAOC mode is entered coming out from GPIO mode the output flip-flop is set to the complement of the EDPOL bit in the EMIOSC[n] register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 675 0x001000 0x001100 0x001000 FLAG pin/register 0x001000 0x001000 0x001000 A1 value 0xxxxxxx 0x001000 Notes: 1. EMIOSA[n] = A2 A2 = A1 according to OU[n] bit Figure 27-21. SAOC example toggling the output flip-flop MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 676 The input pulse width is calculated by subtracting the value in B1 from A2. Figure 27-23 shows how the Unified Channel can be used for input pulse width measurement. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 677 EMIOSA[n] register. Note that even in this case B1 register updates will be blocked after EMIOSA[n] read, thus a second EMIOSB[n] is required in order to release B1 register updates. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 678 After EMIOSB[n] is read, register A1 content is transferred to register B1 and the transfers from B2 to B1 are reenabled to occur at the transfer edges, which is the leading edge in the Figure 27-26 example. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 679 At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator A or B, respectively. Note that the FLAG bit is not affected by these forced operations. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 680 Notes: 1. EMIOSA[n] = A1 (when reading) 2. EMIOSB[n] = B1 (when reading) A2 = A1according to OU[n] bit B2 = B1according to OU[n] bit Figure 27-28. Double action output compare with FLAG set on both matches MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 681 See Figure 27-52 Figure 27-54. • Internal counter clearing on match end (MODE[0:6] = 001001b) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 682 0x000303 0x000200 0x000000 Time FLAG pin/register 0xxxxxxx 0x000303 0x000303 0x000200 0x000200 A1 value 0x000303 Notes: 1. EMIOSA[n] = A1 A2 = A1according to OU[n] bit Figure 27-30. Modulus Counter Up mode example MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 683 A1 values. Register A1 is loaded with A2 register value at the cycle boundary. Thus any value written to A2 register within cycle n will be updated to A1 at MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 684 Thus, A1 is updated with A2 value at the same time that the counter (EMIOSCNT[n]) is loaded with 0x1. The load signal pulse has the MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 685 A1 register indicates the duty cycle and B1 register the frequency. Both A1 and B1 registers are double buffered to MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 686 A1 = 0x1. Note that A1 posedge match signal from cycle n+1 occurs at the same time as B1 negedge MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 687 B2 data written on cycle n were loaded to A1 or B1, respectively, thus generating matches in cycle n+1. Note that the FLAG has a synchronous operation, meaning that it is asserted one system clock cycle after the FLAG set event. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 688 A 0% duty cycle signal is generated if A1 = 0x0 as shown in Figure 27-39 cycle 9. In this case B1 = 0x8 match from cycle 8 occurs at the same time as the A1 = 0x0 match from cycle 9. Please, refer to MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 689 11. [OPWMCB channel] Select time base input through BSL[1:0] bits; 12. [OPWMCB channel] Enter OPWMCB mode; 13. [OPWMCB channel] Set prescaler ratio; 14. [OPWMCB channel] Enable Channel Prescaler; 15. [global] Enable Global Prescaler. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 690 Center Aligned PWM signal. Note that both A1 and B1 register values are changing within the same cycle, which allows to vary at the same time the duty cycle and dead time values. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 691 A1 and the selected time base, the internal counter is set to 0x1 and B1 matches are enabled. When the match between register B1 and the selected time base occurs the output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 692 FORCMA bit set does not set the internal time-base to 0x1 as a regular A1 match. The FLAG bit is not set either in case of a FORCMA or FORCMB or even if both forces are issued at the same time. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 693 100% duty cycle output signal generated by setting A1 = 4 and B1 = 3. In this case the trailing edge is positioned at the boundary of cycle n+1, which is actually considered to belong to cycle n+2 and therefore does not cause the output flip-flip to transition. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 694 A1 or B1 respectively. FLAG bit is not set by the FORCMA and FORCMB operations. At OPWMB mode entry the output flip-flop is set to the value of the EDPOL bit in the EMIOSC[n] register. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 695 B1 = 0x8 negedge signal. In this case A1 match has precedence over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 696 EDPOL bit at B1 match. Note also that if B1 is set to 0x9, for instance, B1 match does not occur, thus a 0% duty cycle signal is generated. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 697 Note that the output pin and flag transitions are based on the posedges of the A1, B1 and A2 match signals. Please, refer to Figure 27-44 Section 27.4.4.1.1.11, Output Pulse Width Modulation Buffered (OPWMB) Mode, for details on match posedge. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 698 EDPOL bit. The transfer from register B2 to B1 is still triggered by the match at comparator A. Figure 27-47 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and duty cycle update on next period update. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 699 2. EMIOSB[n] = B2 for write, B1 for read Figure 27-48. OPWMT with 0% Duty Cycle Figure 27-49 shows the Unified Channel running in OPWMT mode with Trigger Event Generation and 100% duty cycle. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 700 At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge detector. A timing diagram of the input filter is shown in Figure 27-51. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 701 When exiting debug mode or freeze enable bit is cleared (FRZ in the EMIOSMCR or FREN in the EMIOSC[n] register) the channel actions resume, but may be inconsistent until channel enters GPIO mode again. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 702 EMIOSA[n] or EMIOSB[n] were not updated with the correct value before the time base matches the previous contents of EMIOSA[n] or EMIOSB[n]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 703 If MC mode and Clear on Match Start and Internal Clock source are selected, the internal counter behaves as described in Figure 27-54. • If MC mode and Clear on Match End are selected, the internal counter behaves as described in Figure 27-55. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 704 Note 1: When a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of pre scaled clock the counter will start counting. Figure 27-54. Time base generation with internal clock and clear on match start MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 705 7. [timebase channel] Enable Channel Prescaler. 8. [output channel] Disable Channel Prescaler. 9. [output channel] Set A/B register. 10. [output channel] Select timebase input through bits BSL[1:0]. 11. [output channel] Enter output mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 706 PIT block diagram. Peripheral Registers Timer 0 Interrupts Triggers Timer 7 System Clock Figure 27-56. PIT block diagram 27.5.2 Features The main features of this block are: • Timers can generate DMA trigger pulses MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 707 706 channel + 0x04 Current Timer Value Register (CVAL) on page 707 channel + 0x08 Timer Control Register (TCTRL) on page 708 channel + 0x0C Timer Flag Register (TFLG) on page 708 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 708 0 = Timers continue to run in debug mode. 1 = Timers are stopped in debug mode. 27.5.4.3 Timer Load Value Register (LDVAL) This register selects the timeout period for the timer interrupts. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 709 This field represents the current timer value. Note that the timer uses a downcounter. Note: The timer values will be frozen in Debug mode if the FRZ bit is set in the PIT Module Control Register (see Figure 27-2). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 710 0 Timer will be disabled 1 Timer will be active 27.5.4.6 Timer Flag Register (TFLG) This register holds the PIT interrupt flags. Offset: channel_base + 0x0C Access: Read/Write Reset Reset Figure 27-61. Timer Flag Register (TFLG) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 711 This value will then be loaded after the next trigger event (see Figure 27-64). Timer Enabled Disable Re-Enable Start Value = p1 Timer Timer Trigger Event Figure 27-62. Stopping and starting a timer MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 712 5.12 ms/20 ns = 256000 cycles and Timer 3 every 30 ms/20 ns = 1500000 cycles. The value for the LDVAL register trigger would be calculated as (period / clock period) – 1. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 713 PIT_TCTRL1 = TIE; // enable Timer 1 interrupts PIT_TCTRL1 |= TEN; // start timer 1 // Timer 3 PIT_LDVAL3 = 0x0016E35F; // setup timer 3 for 1500000 cycles PIT_TCTRL3 = TEN; // start timer 3 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 714 Chapter 27 Timers This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 715 ——— ADC system ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 716 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 717 Supports DMA transfer of results based on the end of conversion • 6 + 3 analog watchdogs (6 on 10-bit ADC, 3 on 12-bit ADC) with interrupt capability for continuous hardware monitoring MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 718 Trigger PIT6 ADC_1_S[0] (Ch 32) ADC_1_P[15] (Ch 15) 16 precision channels (same pins as ADC 10b) ADC_1_P[0] (Ch 0) INTC 2 interrupts ADC_EOC & ADC_WD Figure 28-1. Implementation of ADC_0 and ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 719 (NSTART bit in the Main Status Register (MSR) is reset). 28.3.1.2 Start of normal conversion The conversion chain starts when the NSTART bit in the Main Configuration Register (MCR) is set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 720 Mode, the MCR[NSTART] bit is not reset. It can be reset by software when the user needs to stop scan mode. In that case, the ADC completes the current scan conversion and, after the last conversion, also resets the MSR[NSTART] bit. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 721 The MSR[JSTART] is automatically set when the Injected conversion starts. At the same time the MCR[JSTART] is reset, allowing the software to program a new start of conversion. In that case the new requested conversion starts after the running injected conversion is completed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 722 After completion of the sampling phase, the evaluation phase starts and all the bits corresponding to the resolution of the ADC are estimated to provide the conversion result. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 723 The total conversion duration is (not including external multiplexing):    T conv T sample T eval ndelay T The timings refer to the unit T , where f = (1/2 × ADC peripheral set clock). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 724 The capacitors field input End of conversion switch is opened Note: Operating conditions — INPLATCH = 0, INPSAMP = 3, INPCMP = 1 and Fadc clk = 20 MHz Figure 28-5. Sampling and conversion timings MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 725 0.500 16.000 1.500 2.031 65.000 Where: INPSAMPLE 8 Where: INPSAMP  6, N = 0.5; INPSAMP > 6, N = 1 ; Must be  500 ns Where: T = (INPSAMP-N)T sample MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 726 Max f Min f ADC_clk ADC_clk Not allowed Not allowed 20 + 4% 13.33 5 + 4% 3.33 Not allowed Not allowed 10 + 4% 6.67 10 + 4% 15 + 4% MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 727 This is useful for resetting information regarding the last converted data or to have more accurate control of conversion speed. During presampling, the ADC samples the internally generated voltage. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 728 The analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in Figure 28-8) specified by upper and lower threshold values named THRH and THRL, respectively. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 729 WDGxH for high threshold violation is set. Thus, the user should avoid that situation as it could lead to misinterpretation of the watchdog interrupts. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 730 The ADC provides several external decode signals to select which external channel has to be converted. In order to take into account the control switching time of the external analog multiplexer, a Decode MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 731 The auto-clock-off feature cannot operate when the digital interface runs at the same rate as the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock will not shut down in IDLE mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 732 28.4 Register descriptions 28.4.1 Introduction MPC5606BK has two ADCs (10-bit ADC_0 and 12-bit ADC_1) and each has specific registers. Table 28-9 lists the ADC_0 registers with their address offsets and reset values. Table 28-9. 10-bit ADC_0 digital registers Base address: 0xFFE0_0000...
Page 733 Channel 9 Data Register (CDR9) on page 763 0x0128 Channel 10 Data Register (CDR10) on page 763 0x012C Channel 11 Data Register (CDR11) on page 763 0x0130 Channel 12 Data Register (CDR12) on page 763 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 734 Channel 55 Data Register (CDR55) on page 763 0x01E0 Channel 56 Data Register (CDR56) on page 763 0x01E4 Channel 57 Data Register (CDR57) on page 763 0x01E8 Channel 58 Data Register (CDR58) on page 763 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 735 Channel 89 Data Register (CDR89) on page 763 0x0268 Channel 90 Data Register (CDR90) on page 763 0x026C Channel 91 Data Register (CDR91) on page 763 0x0270 Channel 92 Data Register (CDR92) on page 763 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 736 Analog Watchdog Out of Range register 1 (AWORR1) on page 775 0x02F8 Analog Watchdog Out of Range register 2 (AWORR2) on page 775 0x2FC–0x02FF Reserved — Table 28-10 lists the ADC_1 registers with their address offsets and reset values. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 737 756 0x0098 Conversion Timing Register 1(CTR1) on page 756 0x009C–0x00A3 Reserved — 0x00A4 Normal Conversion Mask Register 0 (NCMR0) on page 757 0x00A8 Normal Conversion Mask Register 1 (NCMR1) on page 757 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 738 Channel 36 Data Register (CDR36) on page 763 0x0194 Channel 37 Data Register (CDR37) on page 763 0x0198 Channel 38 Data Register (CDR38) on page 763 0x019C Channel 39 Data Register (CDR39) on page 763 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 739 Control logic registers 28.4.2.1 Main Configuration Register (MCR) The Main Configuration Register (MCR) provides configuration settings for the ADC. Address: Base + 0x0000 Access: User read/write Reset Reset Figure 28-9. Main Configuration Register (MCR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 740 If it is set during a scan chain, only the ongoing conversion is aborted and the next conversion is performed as planned. 0 Conversion is not affected 1 Aborts the ongoing conversion MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 741 This status bit is used to signal that a CTU conversion is ongoing. CHADDR Current conversion channel address This status field indicates current conversion channel address. ACKO Auto-clock-off enable This status bit is used to signal if the Auto-clock-off feature is on. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 742 JEOC JECH EOC ECH Reset Figure 28-11. Interrupt Status Register (ISR) Table 28-13. ISR field descriptions Field Description EOCTU End of CTU Conversion interrupt flag When this bit is set, an EOCTU interrupt has occurred. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 743 ADC_1 CEOCFR1 End of conversion pending interrupt for channel 32 to 39 (standard channels) Address: Base + 0x0014 Access: User read/write Reset W w1c Reset Figure 28-12. Channel Pending Register 0 (CEOCFR0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 744 Access: User read/write Reset W w1c Reset Figure 28-13. Channel Pending Register 1 (CEOCFR1) – ADC_0 Address: Base + 0x0018 Access: User read/write Reset Reset Figure 28-14. Channel Pending Register 1 (CEOCFR1) – ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 745 Interrupt Mask Register (IMR) The Interrupt Mask Register (IMR) contains the interrupt enable bits for the ADC. Address: Base + 0x0020 Access: User read/write Reset Reset Figure 28-16. Interrupt Mask Register (IMR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 746 Enable bit for channel 32 to 39 (standard channels) Table 28-17. CIMR[0..2] register description Address: Base + 0x0024 Access: User read/write Reset R CIM Reset Figure 28-17. Channel Interrupt Mask Register 0 (CIMR0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 747 Reset Figure 28-19. Channel Interrupt Mask Register 1 (CIMR1) for ADC_1 Address: Base + 0x002C Access: User read/write R CIM Reset R CIM Reset Figure 28-20. Channel Interrupt Mask Register 2 (CIMR2) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 748 This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold (for[x = 0..5). WDGxL This corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold (for[x = 0..5.) For ADC_1 (12-bit) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 749 (for [x = 0..2]). 28.4.3.6 Watchdog Threshold Interrupt Mask Register (WTIMR) For ADC_0 (10-bit): Address: Base + 0x0034 Access: User read/write Reset Reset Figure 28-23. ADC_0 Watchdog Threshold Interrupt Mask Register (WTIMR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 750 (for [x = 0..2]). When set the interrupt is enabled. 28.4.4 DMA registers 28.4.4.1 DMA Enable Register (DMAE) The DMA Enable (DMAE) register sets up the DMA for use with the ADC. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 751 Enable bits for channel 64 to 95 (external multiplexed channels) ADC_1 DMAR0 Enable bits for channel 0 to 15 (precision channels) ADC_1 DMAR1 Enable bit for channel 32 to 39 (standard channels) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 752 R DMA Reset Figure 28-27. DMA Channel Select Register 1 (DMAR1) for ADC_0 Address: Base + 0x0048 Access: User read/write Reset Reset Figure 28-28. DMA Channel Select Register 1 (DMAR1) for ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 753 Figure 28-29. DMA Channel Select Register 2 (DMAR2) Table 28-25. DMARx field descriptions Field Description DMAn DMA enable When set (DMAn = 1), channel n is enabled to transfer data in DMA mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 754 Low threshold value for channel n. For ADC_1 (12-bit): THRHLR[0..2] Address: Base + 0x0060 (THRHLR0) Base + 0x0064 (THRHLR1) Access: User read/write Base + 0x0068 (THRHLR2) THRH Reset THRL Reset Figure 28-31. ADC_1 Threshold Register THRHLR[0..2] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 755 If bit PRECONV is set, presampling is followed by the conversion. Sampling will be bypassed and conversion of presampled data will be done. 28.4.6.2 Presampling Register (PSR[0..2]) Table 28-29 shows the available channels. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 756 PRES PRES PRES PRES PRES Reset R PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES PRES Reset Figure 28-34. Presampling Register 1 (PSR1) for ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 757 PRES PRES PRES PRES Reset Figure 28-36. Presampling Register 2 (PSR2) Table 28-30. PSR field descriptions Field Description PRESn Presampling enable When set (PRESn = 1), presampling is enabled for channel n. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 758 10 Transition between code 00h and 001h is reached when the A is equal to 0 11 Not used Note: Available only on CTR0. INPCMP Configuration bits for comparison phase duration INPSAMP Configuration bits for sampling phase duration MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 759 Address: Base + 0x00A4 Access: User read/write Reset CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 Reset Figure 28-38. Normal Conversion Mask Register 0 (NCMR0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 760 CH95 CH94 CH93 CH92 CH91 CH90 CH89 CH88 CH87 CH86 CH85 CH84 CH83 CH82 CH81 CH80 Reset CH79 CH78 CH77 CH76 CH75 CH74 CH73 CH72 CH71 CH70 CH69 CH68 CH67 CH66 CH65 CH64 Reset Figure 28-41. Normal Conversion Mask Register 2 (NCMR2) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 761 When set, sampling is enabled for channel n. NOTE The implicit channel conversion priority in the case in which all channels are selected is the following: ADCn_P[0:x], ADCn_S[0:y], ADCn_X[0:z]. The channels always start with 0, the lowest index. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 762 CH59 CH58 CH57 CH56 CH55 CH54 CH53 CH52 CH51 CH50 CH49 CH48 Reset CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32 Reset Figure 28-43. Injected Conversion Mask Register 1 (JCMR1) for ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 763 Field Description Sampling enable When set, sampling is enabled for channel n. 28.4.9 Delay registers 28.4.9.1 Decode Signals Delay Register (DSDR) The Decode Signals Delay Register (DSDR) is implemented only on ADC_0. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 764 DSD = 2; 1 ADC clock cycle delay DSD = 4; 2 ADC clock cycles delay 28.4.9.2 Power-down Exit Delay Register (PDEDR) Address: Base + 0x00C8 Access: User read/write Reset PDED Reset Figure 28-47. Power-down Exit Delay Register (PDEDR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 765 CDR1[32..59] Enable bits of injected sampling for channel 32 to 39 (standard channels) Table 28-39. CDR[0..95] register description Each data register also gives information regarding the corresponding result as described below. For ADC_0 10-bit: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 766 Figure 28-48. Channel Data Register (CDR[0..95]) For ADC_1 12-bit: Address: See Table 28-10 Access: User read-only OVER RESULT [0:1] Reset CDATA[0:11] (MCR[WLSIDE] = 0) Reset CDATA[0:11] (MCR[WLSIDE] = 1) Reset Figure 28-49. Channel Data Register (CDR[0..95]) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 767 Channel watchdog select register for channel 0 to 15 (precision channels) ADC_1 CWSELR[2..3] Not implemented ADC_1 CWSELR[4] Channel watchdog select register for channel 32 to 39 (standard channels) ADC_1 CWSELR[5..11] Not implemented MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 768 THRHLR4 register is selected THRHLR5 register is selected Reserved Reserved Offset: 0x02B4 Access: User read/write WSEL_CH15 WSEL_CH14 WSEL_CH13 WSEL_CH12 Reset WSEL_CH11 WSEL_CH10 WSEL_CH9 WSEL_CH8 Reset Figure 28-51. Channel Watchdog Select Register 1 (CWSELR1) – ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 769 Table 28-44. CWSELR4 field descriptions – ADC_0 Field Description WSEL_CHn See Table 28-42. Offset: 0x02C4 Access: User read/write WSEL_CH47 WSEL_CH46 WSEL_CH45 WSEL_CH44 Reset WSEL_CH43 WSEL_CH42 WSEL_CH41 WSEL_CH40 Reset Figure 28-53. Channel Watchdog Select Register 5 (CWSELR5) – ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 770 Table 28-46. CWSELR6 field descriptions – ADC_0 Field Description WSEL_CHn See Table 28-42. Offset: 0x02CC Access: User read/write Reset WSEL_CH59 WSEL_CH58 WSEL_CH57 WSEL_CH56 Reset Figure 28-55. Channel Watchdog Select Register 7 (CWSELR7) – ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 771 Table 28-48. CWSELR8 field descriptions – ADC_0 Field Description WSEL_CHn See Table 28-42. Offset: 0x02D4 Access: User read/write WSEL_CH79 WSEL_CH78 WSEL_CH77 WSEL_CH76 Reset WSEL_CH75 WSEL_CH74 WSEL_CH73 WSEL_CH72 Reset Figure 28-57. Channel Watchdog Select Register 9 (CWSELR9) – ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 772 Table 28-50. CWSELR10 field descriptions – ADC_0 Field Description WSEL_CHn See Table 28-42. Offset: 0x02DC Access: User read/write WSEL_CH95 WSEL_CH94 WSEL_CH93 WSEL_CH92 Reset WSEL_CH91 WSEL_CH90 WSEL_CH89 WSEL_CH88 Reset Figure 28-59. Channel Watchdog Select Register 11 (CWSELR11) – ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 773 10 THRHLR2 register is selected 11 Reserved Offset: 0x02B4 Access: User read/write WSEL_CH15 WSEL_CH14 WSEL_CH13 WSEL_CH12 Reset WSEL_CH11 WSEL_CH10 WSEL_CH9 WSEL_CH8 Reset Figure 28-61. Channel Watchdog Select Register 1 (CWSELR1) – ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 774 Table 28-54. CWSELR4 field descriptions – ADC_1 Field Description WSEL_CHn See Table 28-52. Offset: 0x02C4 Access: User read/write WSEL_CH47 WSEL_CH46 WSEL_CH45 WSEL_CH44 Reset WSEL_CH43 WSEL_CH42 WSEL_CH41 WSEL_CH40 Reset Figure 28-63. Channel Watchdog Select Register 5 (CWSELR5) – ADC_1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 775 Address: Base + 0x02E0 Access: User read/write Reset R CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN Reset Figure 28-64. Channel Watchdog Enable Register 0 (CWENR0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 776 CWEN CWEN CWEN CWEN CWEN Reset R CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN CWEN Reset Figure 28-67. Channel Watchdog Enable Register 2 (CWENR2) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 777 Figure 28-68. Analog Watchdog Out of Range Register 0 (AWORR0) Address: Base + 0x02F4 Access: User read/write Reset W w1c Reset Figure 28-69. Analog Watchdog Out of Range Register 1 (AWORR1) – ADC_0 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 778 W w1c Reset Figure 28-71. Analog Watchdog Out of Range Register 2 (AWORR2) Table 28-58. AWORRx field descriptions Field Description AWORR_CHn When set, indicates channel n converted data is out of range MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 779 Figure 29-1. Cross Triggering Unit block diagram 29.4 Memory map and register descriptions The CTU registers are listed in Table 29-1. Every register can have 32-bit access. The base address of the CTU is 0xFFE6_4000. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 780 These registers contain the ADC channel number to be converted when the timer event occurs. The CLR_FLAG is used to clear the respective timer event flag by software (this applies only to the PIT as the eMIOS flags are automatically cleared by the CTU). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 781 0 Channel_4 eMIOS 0 Channel_5 eMIOS 0 Channel_6 eMIOS 0 Channel_7 eMIOS 0 Channel_8 eMIOS 0 Channel_9 eMIOS 0 Channel_10 eMIOS 0 Channel_11 eMIOS 0 Channel_12 eMIOS 0 Channel_13 eMIOS 0 Channel_14 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 782 1 Channel_5 eMIOS 1 Channel_6 eMIOS 1 Channel_7 eMIOS 1 Channel_8 eMIOS 1 Channel_9 eMIOS 1 Channel_10 eMIOS 1 Channel_11 eMIOS 1 Channel_12 eMIOS 1 Channel_13 eMIOS 1 Channel_14 eMIOS 1 Channel_15 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 783 The channel value stored in an event configuration register is demultiplexed to 7 bits and then provided to the ADC. The mapping of the channel number value to the corresponding ADC channel is provided in Table 29-3. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 784 ADC0_S[3] CH35 ADC1_S[3] CH35 ADC0_S[4] CH36 ADC1_S[4] CH36 ADC0_S[5] CH37 ADC1_S[5] CH37 ADC0_S[6] CH38 ADC1_S[6] CH38 ADC0_S[7] CH39 ADC1_S[7] CH39 ADC0_S[8] CH40 ADC0_S[9] CH41 ADC0_S[10] CH42 ADC0_S[11] CH43 ADC0_S[12] CH44 ADC0_S[13] CH45 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 785 CTU channel mapping should be taken into consideration when programming an event configuration register. For example, if the channel value of any event configuration register is programmed to 16, it will actually correspond to ADC channel 32 and conversion will occur for this channel. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 786 Chapter 29 Cross Triggering Unit (CTU) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 787 ——— Memory ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
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Page 789 The primary function of the flash memory module is to serve as electrically programmable and erasable nonvolatile memory. Nonvolatile memory may be used for instruction and/or data storage. The module is a nonvolatile solid-state silicon memory device consisting of: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 790 One-Time Programmable (OTP) area in Test Flash block Boot sectors 30.3 Block diagram The flash memory module contains one Matrix Module, composed of a single bank (Bank 0) normally used for code storage. RWW operations are not possible. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 791 The flash memory module supports fault tolerance through Error Correction Code (ECC) or error detection, or both. The ECC implemented within the flash memory module will correct single bit failures and detect double bit failures. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 792 0x00000000–0x00007FFF 32 KB LLK0 0x00008000–0x0000BFFF 16 KB LLK1 0x0000C000–0x0000FFFF 16 KB LLK2 0x00010000–0x00017FFF 32 KB LLK3 0x00018000–0x0001FFFF 32 KB LLK4 0x00020000–0x0003FFFF 128 KB LLK5 0x00040000–0x0005FFFF 128 KB MLK0 0x00060000–0x0007FFFF 128 KB MLK1 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 793 A TestFlash block is available in both the CFlash and DFlash modules. The TestFlash block exists outside the normal address space and is programmed and read independently of the other blocks. The independent MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 794 Erase of the TestFlash block is always locked. Programming of the TestFlash block has similar restrictions as the array in terms of how ECC is calculated. Only one programming operation is allowed per 64-bit ECC segment. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 795 In User mode, the flash memory module may be read and written (register writes and interlock writes), programmed, or erased. The default state of the flash memory module is read. The main, shadow and test address space can be read only in the read state. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 796 Reset terminates all operations and forces the flash memory module into User mode ready to receive accesses. Reset and power-off must not be used as a systematic way to terminate a program or erase operation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 797 If the flash memory module enters low power mode during a program operation, the operation will be in any case completed and the low power mode will be entered only after the programming end. It is forbidden to enter power-down mode when the low power mode is active. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 798 Table 30-8. DFlash registers Address offset Register name Location 0x0000 DFlash Module Configuration Register (DFLASH_MCR) on page 834 0x0004 DFlash Low/Mid Address Space Block Locking Register on page 839 (DFLASH_LML) 0x0008 Reserved — MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 799 MCR (CFLASH_MCR or DFLASH_MCR). 30.5.1 CFlash register description 30.5.1.1 CFlash Module Configuration Register (CFLASH_MCR) The CFlash Module Configuration Register is used to enable and monitor all modify operations of the flash memory module. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 800 If EER is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of EER) were correct. 0 Reads are occurring normally. 1 An ECC double error occurred during a previous read. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 801 , time equals to Erase Suspend Latency) after a 0-to-1 ESUS transition of ESUS, which suspends an erase operation. 0 Flash memory is executing a high voltage operation. 1 Flash memory is not executing a high voltage operation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 802 ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0 Flash memory is not executing an erase sequence. 1 Flash memory is executing an erase sequence. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 803 1 Flash memory is enabled to perform an high voltage operation. Table 30-10. Array space size SIZE Array space size 128 KB 256 KB 512 KB 1024 KB 1536 KB Reserved (2048 KB) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 804 Table 30-13. CFLASH_MCR bits set/clear priority levels Priority level CFLASH_MCR bits ESUS If the user attempts to write two or more CFLASH_MCR bits simultaneously then only the bit with the lowest priority level is written. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 805 Defined by CFLASH_NVLML at CFlash Test sector address 0x403DE8. This location is user OTP (One-Time Programmable). The CFLASH_NVLML register influences only the R/W bits of the CFLASH_LML register. Figure 30-4. CFlash Low/Mid Address Space Block Locking Register (CFLASH_LML) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 806 TSLK is not writable unless LME is high. 0 Test/Shadow address space block is unlocked and can be modified (also if CFLASH_SLL[STSLK] = 0). 1 Test/Shadow address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 807 TestFlash that contains the default reset value for CFLASH_LML. During the reset phase of the flash memory module, the CFLASH_NVLML register content is read and loaded into the CFLASH_LML. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 808 TSLK is not writable unless LME is high. 0 Test/Shadow address space block is unlocked and can be modified (also if CFLASH_SLL[STSLK] = 0). 1 Test/Shadow Address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 809 1 Low address space block is locked and cannot be modified. 30.5.1.3 CFlash High Address Space Block Locking Register (CFLASH_HBL) The CFLASH_HBL register provides a means to protect blocks from being modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 810 In the 544 KB Flash module bits HLK11-8 are read-only and locked at 1. HLK is not writable unless HBE is high. 0 High address space block is unlocked and can be modified. 1 High address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 811 The CFLASH_NVHBL register is a 64-bit register, of which the 32 most significant bits 63:32 are “don’t care” and eventually used to manage ECC codes. Offset: 0x403DF0 Access: Read/write R HBE Reset Reset Figure 30-7. CFlash Nonvolatile High Address Space Block Locking Register (CFLASH_NVHBL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 812 These bits, along with bits in the CFLASH_LML register, determine if the block is locked from program or erase. An OR of CFLASH_LML and CFLASH_SLL determines the final lock status. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 813 STSLK is not writable unless SLE is high. 0 Test/Shadow address space block is unlocked and can be modified (also if CFLASH_LML[TSLK] = 0). 1 Test/Shadow address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 814 SLK is not writable unless SLE is high. 0 Low address space block is unlocked and can be modified (also if CFLASH_LML[LLK] = 0). 1 Low address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 815 The CFLASH_NVSLL register is a 64-bit register, of which the 32 most significant bits 63:32 are “don’t care” and are used to manage ECC codes. Offset: 0x403DF8 Access: Read/write R SLE Reset Reset Figure 30-9. CFlash Nonvolatile Secondary Low/mid address space block Locking register (CFLASH_NVSLL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 816 STSLK is not writable unless SLE is high. 0 Test/Shadow address space block is unlocked and can be modified (also if CFLASH_LML[TSLK] = 0). 1 Test/Shadow address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 817 SLK is not writable unless SLE is high. 0 Low address space block is unlocked and can be modified (also if CFLASH_LML[LLK] = 0). 1 Low address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 818 0, and register writes will have no effect. Bits LSL[15:6] are read-only and locked at 0. 0 Low address space block is not selected for erase. 1 Low address space block is selected for erase. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 819 In the 544 KB Flash module, bits HSL11-8 are read-only and locked at 0. 0 High address space block is not selected for erase. 1 High address space block is selected for erase. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 820 Address of first ECC double error CFLASH_MCR[RWE] = 1 Address of first RWW error CFLASH_MCR[PEG] = 0 Address of first FPEC error CFLASH_MCR[EDC] = 1 Address of first ECC single error correction MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 821 This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 822 Once completed, AID will be set to indicate that the array integrity check is complete. At this time the MISR (CFLASH_UMISR0-4) can be checked. 0 Array integrity check is on-going. 1 Array integrity check is done. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 823 The CFLASH_UT2 register allows to enable the checks on the ECC logic related to the 32 MSB of the double word. The User Test 2 Register is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 824 The User Multiple Input Signature Register 0 represents the bits 31:0 of the whole 144 bits word (2 double words including ECC). The CFLASH_UMISR0 Register is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 825 The CFLASH_UMISR1 represents the bits 63:32 of the whole 144 bits word (2 double words including ECC). The CFLASH_UMISR1 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 826 The CFLASH_UMISR2 represents the bits 95:64 of the whole 144 bits word (2 double words including ECC). The CFLASH_UMISR2 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 827 The CFLASH_UMISR3 represents the bits 127:96 of the whole 144 bits word (2 double words including ECC). The CFLASH_UMISR3 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 828 4:5 and 20:21 of MISR are respectively the double and single ECC error detection for odd and even double word. The CFLASH_UMISR4 is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 829 30.5.1.16 CFlash Nonvolatile Private Censorship Password 0 Register (NVPWD0) The Nonvolatile Private Censorship Password 0 register contains the 32 LSB of the password used to validate the censorship information contained in NVSCC0–1 registers. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 830 The Nonvolatile Private Censorship Password 1 register contains the 32 MSB of the password used to validate the censorship information contained in NVSCC0–1 registers. Offset: 0x203DDC Access: Read/write PWD[63:48] Reset PWD[47:32] Reset Figure 30-22. CFlash Nonvolatile Private Censorship Password 1 Register (NVPWD1) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 831 The parts are delivered uncensored to the user. Offset: 0x203DE0 Access: Read/write SC[15:0] Reset CW[15:0] Reset Figure 30-23. CFlash Nonvolatile System Censorship Control 0 register (NVSCC0) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 832 These bits represent the 16 MSB of the Censorship Control Word (CCW). If CW15-0 = 0x55AA and NVSCC1 = NVSCC0 the Censored Mode is disabled.   If CW15-0 0x55AA or NVSCC1 NVSCC0 the Censored Mode is enabled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 833 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V Default manufacturing value before flash memory initialization is 1 (3.3 V), which should ensure correct minimum slope for boundary scan. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 834 The value of the LAS field corresponds to the configuration of the low address space. See Table 30-39. Mid Address Space The value of the MAS field corresponds to the configuration of the mid address space. See Table 30-40. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 835 , time equals to Erase Suspend Latency) after a 0-to-1 ESUS transition of ESUS, which suspends an erase operation. 0 Flash memory is executing a high voltage operation. 1 Flash memory is not executing a high voltage operation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 836 ERS can be cleared by the user only when ESUS and EHV are low and DONE is high. ERS is cleared on reset. 0 Flash memory is not executing an erase sequence. 1 Flash memory is executing an erase sequence. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 837 1 Flash memory is enabled to perform an high voltage operation. Table 30-38. Array space size SIZE Array space size 128 KB 256 KB 512 KB Reserved (1024 KB) Reserved (1536 KB) Reserved (2048 KB) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 838 Table 30-41. DFLASH_MCR bits set/clear priority levels Priority level DFLASH_MCR bits ESUS If the user attempts to write two or more DFLASH_MCR bits simultaneously then only the bit with the lowest priority level is written. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 839 Defined by DFLASH_NVLML at DFlash Test sector address 0xC03DE8. This location is user OTP (One-Time Programmable). The DFLASH_NVLML register influences only the R/W bits of the DFLASH_LML register. Figure 30-27. DFlash Low/Mid Address Space Block Locking Register (DFLASH_LML) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 840 LLK is not writable unless LME is high. 0 Low address space block is unlocked and can be modified (also if DFLASH_SLL[SLK] = 0). 1 Low address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 841 The DFLASH_NVLML register is a 64-bit register, of which the 32 most significant bits 63:32 are “don’t care” and are used to manage ECC codes. Offset: 0xC03DE8 Access: Read/write R LME TSLK Reset Reset Figure 30-28. DFlash Nonvolatile Low/Mid address space block Locking register (DFLASH_NVLML) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 842 LLK is not writable unless LME is high. 0 Low address space block is unlocked and can be modified (also if DFLASH_SLL[SLK] = 0). 1 Low address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 843 Defined by DFLASH_NVSLL at DFlash Test Sector Address 0xC03DF8. This location is user OTP (One-Time Programmable). The DFLASH_NVSLL register influences only the R/W bits of the DFLASH_SLL register. Figure 30-29. DFlash Secondary Low/Mid Address Space Block Locking register (DFLASH_SLL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 844 SLK is not writable unless SLE is high. 0 Low address space block is unlocked and can be modified (also if DFLASH_LML[LLK] = 0). 1 Low address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 845 The DFLASH_NVSLL register is a 64-bit register, of which the 32 most significant bits 63:32 are “don’t care” and are used to manage ECC codes. Offset: 0xC03DF8 Access: Read/write R SLE Reset Reset Figure 30-30. DFlash Nonvolatile Secondary Low/mid address space block Locking register (DFLASH_NVSLL) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 846 SLK is not writable unless SLE is high. 0 Low address space block is unlocked and can be modified (also if DFLASH_LML[LLK] = 0). 1 Low address space block is locked and cannot be modified. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 847 DFlash Address Register (DFLASH_ADR) The DFLASH_ADR provides the first failing address in the event module failures (ECC, RWW or FPEC) occur or the first address at which an ECC single error correction occurs. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 848 Address of first ECC single error correction 30.5.2.6 DFlash User Test 0 register (DFLASH_UT0) The User Test Registers provide the user with the ability to test features on the flash memory module. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 849 This bit can be written and its value can be read back, but there is no function associated. This bit is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 850 Once completed, AID will be set to indicate that the array integrity check is complete. At this time the MISR (DFLASH_UMISR0-4) can be checked. 0 Array integrity check is on-going. 1 Array integrity check is done. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 851 The DFLASH_UT2 register allows to enable the checks on the ECC logic related to the 32 MSB of the double word. The User Test 2 Register is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 852 The DFLASH_UMISR0 represents the bits 31:0 of the whole 144 bits word (2 double words including ECC). The DFLASH_UMISR0 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 853 The DFLASH_UMISR1 represents the bits 63:32 of the whole 144 bits word (2 double words including ECC). The DFLASH_UMISR1 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 854 The DFLASH_UMISR2 represents the bits 95:64 of the whole 144 bits word (2 double words including ECC). The DFLASH_UMISR2 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 855 The DFLASH_UMISR3 represents the bits 127:96 of the whole 144 bits word (2 double words including ECC). The DFLASH_UMISR3 is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 856 ECC bits for the even double word; bits 27-264:5 and 11-1020:21 of MISR are respectively the double and single ECC error detection for odd and even double word. The DFLASH_UMISR4 Register is not accessible whenever DFLASH_MCR[DONE] or DFLASH_UT0[AID] are low: reading returns indeterminate data while writing has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 857 MCR[RWE] will be automatically set. This means that the flash memory module is not fetchable when a modify operation is active and these commands must be executed from another memory (internal SRAM or another flash memory module). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 858 A flash memory program sequence operates on any double word within the flash memory core. As many as two words within the double word may be altered in a single program operation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 859 MCR[PEAS] field to be set/cleared. An interlock write must be performed before setting MCR[EHV]. The user may terminate a program sequence by clearing MCR[PGM] prior to setting MCR[EHV]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 860 3. Write to any address in flash memory. This is referred to as an erase interlock write. 4. Write a logic 1 to the MCR[EHV] bit to start the internal erase sequence or skip to step 9 to terminate. 5. Wait until the MCR[DONE] bit goes high. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 861 The user must wait until MCR[DONE] = 1 before the module is suspended and further actions are attempted. MCR[DONE] will go high no more than t after MCR[ESUS] is set to 1. ESUS MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 862 MISR through five different read accesses at the same location. The whole check is done through five complete scans of the memory address space: 1. The first pass will scan only bits 31:0 of each page. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 863 = UMISR2; /* Read UMISR2 content*/ data3 = UMISR3; /* Read UMISR3 content*/ data4 = UMISR4; /* Read UMISR4 content*/ = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */ MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 864 UMISR0 = 0x00000000; /* Reset UMISR0 content */ UMISR1 = 0x00000000; /* Reset UMISR1 content */ UMISR2 = 0x00000000; /* Reset UMISR2 content */ UMISR3 = 0x00000000; /* Reset UMISR3 content */ MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 865 /* Loop to wait for AID=1 */ { tmp = UT0; /* Read UT0 */ } while ( !(tmp & 0x00000001) ); data0 = UMISR0; /* Read UMISR0 content (expected 0x55555555) */ MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 866 Table 30-58. Bit manipulation: double words with the same ECC value Double word ECC all 1s no error 0xFFFF_FFFF_FFFF_FFFF 0xFF 0xFFFF_FFFF_FFFF_0000 0xFF 0xFFFF_FFFF_0000_FFFF 0xFF 0xFFFF_0000_FFFF_FFFF 0xFF 0x0000_FFFF_FFFF_FFFF 0xFF 0xFFFF_FFFF_0000_0000 0xFF 0xFFFF_0000_FFFF_0000 0xFF 0x0000_FFFF_FFFF_0000 0xFF 0xFFFF_0000_0000_FFFF 0xFF 0x0000_FFFF_0000_FFFF 0xFF MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 867 An alternate means to enable software locking for blocks of low address space only is through the SLL. All these registers have a nonvolatile image stored in TestFlash (NVLML, NVSLL), so that the locking information is kept on reset. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 868 A block diagram of the e200z0h Power Architecture reduced product platform (RPP) reference design is shown below in Figure 30-41 with the platform flash memory controller module and its attached off-platform flash memory arrays highlighted. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 869 AHB-to-IPS/APB bus controller (PBRIDGE) for access to on- and off-platform slave modules • Interrupt Controller (INTC) • 4-channel System Timers (STM) • Software Watchdog Timer (SWT) • Error Correction Status Module (ECSM) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 870 The following list summarizes the key features of the platform flash memory controller: • Dual array interfaces support up to a total of 16 MB of flash memory, partitioned as two separate 8 MB banks MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 871 The system memory map defines one code flash memory array and one data flash memory array. See Table 30-59. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 872 30-60. The base address of the controller is 0xC3F8_8000. Table 30-60. Platform flash memory controller 32-bit memory map Address offset Register Location 0x1C Platform Flash Configuration Register 0 (PFCR0) on page 873 MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 873 876 0x24 Platform Flash Access Protection Register (PFAPR) on page 877 See the MPC5606BK data sheet for detailed settings for different values of frequency. 30.7.2.2 Register description This section details the individual registers of the platform flash memory controller.
Page 874 100 Generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt This field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 875 0 The page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 The page buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 876 This field is ignored in single bank flash memory configurations. Note: The Platform Flash Memory Controller does not support Write Wait-State Control since this capability is not supported by the flash memory array. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 877 (bank0) array at reset. To temporarily change the values of any of the fields in the PFAPR, a write to the IPS-mapped register is performed. To change the values loaded into the PFAPR at reset, the word MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 878 AHB master. This field is further qualified by the PFCR0[B0_Px_DPFE, B0_Px_IPFE, Bx_Py_BFE] bits. For master numbering, see Table 19-1. 0 Prefetching may be triggered by this master 1 No prefetching may be triggered by this master MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 879 The NVPFAPR register is a 64-bit register, of which the 32 most significant bits 63:32 are “don’t care” and are used to manage ECC codes. Offset: 0x203E00 Access: Read/write Reset M2AP M0AP Reset Figure 30-45. Nonvolatile Platform Flash Access Protection Register (NVPFAPR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 880 Read cycles – Buffer miss Read cycles from the flash memory array are initiated by the platform flash memory controller. The platform flash memory controller then waits for the programmed number of read wait-states before MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 881 The platform flash memory controller does not support access pipelining since this capability is not supported by the flash memory array. As a result, the APC (Address Pipelining Control) field must be the same value as the RWSC (Read Wait-State Control). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 882 5. Busy AHB — The buffer is currently being used to satisfy an AHB burst read. 6. Busy Fill — The buffer has been allocated to receive data from the flash memory array, and the array access is still in progress. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 883 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. In the second configuration, buffers 0, 1, and 2 are allocated for instruction fetches and buffer 3 reserved for data accesses. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 884 Depending on the specific hardware configuration, the reporting of a single-bit ECC event may generate an ECC alert interrupt. In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ECC event. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 885 As detailed above, a total of four interrupt requests are associated with the stall-while-write functionality. These interrupt requests are captured as part of ECSM’s interrupt register and logically summed together to form a single request to the interrupt controller. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 886 Table 30-67 shows the relationship of haddr[25:24] to the number of additional wait-states. These are applied in addition to those specified by haddr[28:26], and thus extend the total wait-state specification capability. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 887 Chapter 30 Flash Memory Table 30-67. Extended additional wait-state encoding Memory address Additional wait-states haddr[25:24] (added to those specified by haddr[28:26]) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 888 Chapter 30 Flash Memory This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 889 0x4000_0000 (Base) — 80 KB The internal SRAM has no registers. Registers for the SRAM ECC are located in the ECSM [see Chapter 34, Error Correction Status Module (ECSM), for more information]. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 890 SRAM operation (valid operation during the preceding clock) • Wait states — Lists the number of wait states (bus clocks) the operation requires, which depends on the combination of the current and previous operation MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 891 To use the SRAM, the ECC must check all bits that require initialization after power on. All writes must specify an even number of registers performed on 32-bit word-aligned boundaries. If the write is not the MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 892 Chapter 31 Static RAM (SRAM) entire 32 bits (8 or 16 bits), a read / modify / write operation is generated that checks the ECC value upon the read. See Section 31.4, SRAM ECC mechanism. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 893 ——— Integrity ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 894 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 895 Restrict write accesses for the module under protection to supervisor mode only • Lock registers for first 6 KB of memory-mapped address space • Address mirror automatically sets corresponding lock bit • Once configured lock bits can be protected from changes MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 896 X in the same cycle as the register at address X is written. Not all registers in area 1 need to have protection defined by associated soft lock bits. For unprotected registers MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 897 Soft Lock Bit Register 1535 (SLBR1535): soft lock bits 6140-6143 0x3E00–0x3FFB Reserved — 0x3FFC Global Configuration Register (GCR) on page 899 NOTE Reserved registers in area #2 will be handled according to the protected IP (module under protection). MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 898 SLB3 can block accesses to MR[n × 4 + 3] 1 Associated MRn byte is locked against write accesses 0 Associated MRn byte is unprotected and writable Figure 32-3 gives some examples how SLBRn.SLB and MRn go together. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 899 32.5.2.4 Global Configuration Register (GCR) This register is used to make global configurations related to register protection. Address 0x3FFC Access: Read Always Supervisor write Reset Reset Figure 32-4. Global Configuration Register (GCR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 900 • Modify the SLBRn.SLBm directly by writing to area #4 • Set the SLBRn.SLBm bit(s) by writing to the mirror module space (area #3) Both methods are explained in the following sections. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 901 In the example on the left side of Figure 32-6 the data written to SLBRn.SLB[0] is mirrored to SLBRn.SLB[1] and the data written to SLBRn.SLB[2] is mirrored to SLBRn.SLB[3] as for both registers the write enables are set. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 902 Enable locking via mirror module space (area #3) It is possible to enable locking for a register after writing to it. To do so the mirrored module address space must be used. Figure 32-9 shows one example: MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 903 Section 32.6.2.2, Enable locking via mirror module space (area #3) is only possible as long as the bit GCR.HLB is cleared. Once this bit is set, the locking bits can no longer be modified until there is a system reset. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 904 In summary, after reset, locking for all MRn registers is disabled. The registers can be accessed in Supervisor Mode only. 32.8 Protected registers For MPC5606BK the Register Protection module protects the registers shown in Table 32-5. Table 32-5. Protected registers...
Page 905 SIUL PCR36 C3F90000 bits[0:15] SIUL PCR37 C3F90000 bits[0:15] SIUL PCR38 C3F90000 bits[0:15] SIUL PCR39 C3F90000 bits[0:15] SIUL PCR40 C3F90000 bits[0:15] SIUL PCR41 C3F90000 bits[0:15] SIUL PCR42 C3F90000 bits[0:15] SIUL PCR43 C3F90000 bits[0:15] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 906 SIUL PCR92 C3F90000 bits[0:15] SIUL PCR93 C3F90000 bits[0:15] SIUL PCR94 C3F90000 bits[0:15] SIUL PCR95 C3F90000 bits[0:15] SIUL PCR96 C3F90000 bits[0:15] SIUL PCR97 C3F90000 bits[0:15] SIUL PCR98 C3F90000 bits[0:15] SIUL PCR99 C3F90000 bits[0:15] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 907 SIUL PCR131 C3F90000 bits[0:15] SIUL PCR132 C3F90000 bits[0:15] SIUL PCR133 C3F90000 bits[0:15] SIUL PCR134 C3F90000 bits[0:15] SIUL PCR135 C3F90000 bits[0:15] SIUL PSMI0_3 C3F90000 bits[0:7] SIUL PSMI4_7 C3F90000 bits[0:7] SIUL PSMI8_11 C3F90000 bits[0:7] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 908 1030 bits[0:31] SIUL IFMC13 C3F90000 1034 bits[0:31] SIUL IFMC14 C3F90000 1038 bits[0:31] SIUL IFMC15 C3F90000 103C bits[0:31] SIUL IFMC16 C3F90000 1040 bits[0:31] SIUL IFMC17 C3F90000 1044 bits[0:31] SIUL IFMC18 C3F90000 1048 bits[0:31] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 909 C3FDC000 bits[0:31] MC ME ME_RUN_PC7 C3FDC000 bits[0:31] MC ME ME_LP_PC0 C3FDC000 bits[0:31] MC ME ME_LP_PC1 C3FDC000 bits[0:31] MC ME ME_LP_PC2 C3FDC000 bits[0:31] MC ME ME_LP_PC3 C3FDC000 bits[0:31] MC ME ME_LP_PC4 C3FDC000 bits[0:31] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 910 MC RGM RGM_FEAR C3FE4000 bits[0:15] MC RGM RGM_DEAR C3FE4000 bits[0:15] MC RGM RGM_FESS C3FE4000 bits[0:15] MC RGM RGM_STDBY C3FE4000 bits[0:15] MC RGM RGM_FBRE C3FE4000 bits[0:15] Power Control Unit, 2 registers to protect MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 911 Chapter 32 Register Protection Table 32-5. Protected registers (continued) Protected Module base Register Protected Module Register size (bits) address offset bits MC PCU PCONF2 C3FE8000 bits[0:31] MC PCU PCONF3 C3FE8000 bits[0:31] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 912 Chapter 32 Register Protection This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 913 SWT will continue from the state it was before entering this mode. The software watchdog is not available during standby. On exit from standby, the SWT behaves in a usual “out of reset” situation. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 914 0xHHHH, and 0xHHHH_HHHH, where H is a hexadecimal digit, indicate 8-, 16-, and 32-bit registers, respectively. In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for more information. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 915 1 Windowed mode, the service sequence is only valid when the down counter is less than the value in the SWT_WN register. Interrupt Then Reset. 0 Generate a reset on a time-out. 1 Generate an interrupt on an initial time-out, reset on a second consecutive time-out. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 916 1 SWT_CR, SWT_TO, SWT_WN, and SWT_SK are read-only registers. Clock Selection. Selects the SIRC oscillator clock that drives the internal timer. CSL bit can be written.The status of the bit has no effect on counter clock selection on MPC5606BK device.
Page 917 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-4. SWT Window Register (SWT_WN) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 918 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 33-6. SWT Counter Output Register (SWT_CO) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 919 0x100, in which case the time-out period is set to 0x100. This time-out period is loaded into an internal 32-bit down counter when the SWT is enabled and each time a valid service sequence is written. The MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 920 SWT_CR[ITR] bit is not set, a reset is generated immediately on a time-out. If the SWT_CR[ITR] bit is set, an initial time-out causes the SWT to generate an interrupt and load the down counter with the time-out MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 921 Watchdog is disabled at the start of BAM execution. In the case of an unexpected issue during BAM execution, the CPU may be stalled and an external reset needs to be generated to recover. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 922 Chapter 33 Software Watchdog Timer (SWT) This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 923 The Error Correction Status Module does not include any logic that provides access control. Rather, this function is supported using the standard access control logic provided by the IPS controller. Table 34-1 shows the ECSM’s memory map. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 924 Register description Attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 925 The IOPMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS peripheral modules connected to the primary IPI slave bus controller. The state of this register is defined MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 926 Description IPS Module Configuration MC[n] = 0 if an IPS module connection to decoded slot n is absent MC[n] = 1 if an IPS module connection to decoded slot n is present MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 927 0 A flash bank 1 stall has not occurred. 1 A flash bank 1 stall has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0 has no effect. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 928 ECC Error Generation Register (EEGR) • Platform Flash ECC Address Register (PFEAR) • Platform Flash ECC Master Number Register (PFEMR) • Platform Flash ECC Attributes Register (PFEAT) • Platform Flash ECC Data Register (PFEDR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 929 ESR[F1BC]. The address, attributes, and data are also captured in the PFEAR, PFEMR, PFEAT, and PFEDR registers. 0 Reporting of single-bit flash corrections is disabled. 1 Reporting of single-bit flash corrections is enabled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 930 ESR[FNCE]. The faulting address, attributes, and data are also captured in the PFEAR, PFEMR, PFEAT, and PFEDR registers. 0 Reporting of non-correctable flash errors is disabled. 1 Reporting of non-correctable flash errors is enabled. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 931 3. Re-read the ESR and verify the current contents matches the original contents. If the two values are different, go back to step 1 and repeat. 4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 932 ECC, most notably the SRAM. This capability is provided for two purposes: • It provides a software-controlled mechanism for injecting errors into the memories during data writes to verify the integrity of the ECC logic. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 933 This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 0 No SRAM single 1-bit data inversion is generated. 1 One 1-bit data inversion in the SRAM is generated. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 934 ERRBIT = 65, then ECC Parity[1] of the odd bank is inverted if ERRBIT = 70, then ECC Parity[6] of the odd bank is inverted For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 935 Figure 34-9. Platform Flash ECC Address Register (PFEAR) Table 34-10. PFEAR field descriptions Field Description FEAR Flash ECC Address Register This 32-bit register contains the faulting access address of the last, properly enabled flash ECC event. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 936 — — — — — — Figure 34-11. Platform Flash ECC Attributes Register (PFEAT) Table 34-12. PFEAT field descriptions Field Description WRITE AMBA-AHB HWRITE 0 AMBA-AHB read access 1 AMBA-AHB write access MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 937 Flash ECC Data Register This 32-bit register contains the data associated with the faulting access of the last, properly enabled flash ECC event. The register contains the data value taken directly from the data bus. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 938 This register can only be read from the IPS programming model; any attempted write is ignored. Offset: 0x65 Access: Read RESR Reset: — — — — — — — — Figure 34-14. Platform RAM ECC Syndrome Register (PRESR) MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 939 DATA ODD BANK[25] 0x18 DATA ODD BANK[24] 0x1a DATA ODD BANK[23] 0x1c DATA ODD BANK[22] 0x50 DATA ODD BANK[21] 0x20 ECC ODD[5] 0x22 DATA ODD BANK[20] 0x24 DATA ODD BANK[19] 0x26 DATA ODD BANK[18] MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 940 ECC Status Register to be asserted. Chapter 19, Crossbar Switch (XBAR), for a listing of XBAR bus master numbers. This register can only be read from the IPS programming model; any attempted write is ignored. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 941 Protection[3]: Cacheable 0 = Non-cacheable, 1 = Cacheable Protection[2]: Bufferable 0 = Non-bufferable, 1 = Bufferable Protection[1]: Mode 0 = User mode, 1 = Supervisor mode Protection[0]: Type 0 = I-Fetch, 1 = Data MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 942 SRAM ECC event. The register contains the data value taken directly from the data bus. 34.4.3 Register protection Logic exists that restricts accesses to INTC, ECSM, MPU, STM, and SWT to supervisor mode only. Accesses in User mode are not possible. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 943 ——— Debug ——— MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 944 This page is intentionally left blank. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 945 IEEE 1149.1-2001 standard. In addition, instructions can be executed that allow the Test Access Port (TAP) to be shared with other modules on the MCU. All data input to and output from the JTAGC is communicated in serial format. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 946 The boundary scan register is external to JTAGC but can be accessed by JTAGC TAP through EXTEST,SAMPLE,SAMPLE/PRELOAD instructions. The functionality of each TEST mode is explained in more detail in Section 35.8.4, JTAGC instructions. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 947 The JTAGC uses a 5-bit instruction register as shown in Table 35-2. The instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 948 0–3 Part revision number. Contains the revision number of the device. This field changes with each revision of the device or module. 4–9 Design center. For the MPC5606BK this value is 0x1A. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 949 Table 35-2. Device identification register field descriptions Field Description 10–19 Part identification number. Contains the part number of the device. For the MPC5606BK, this value is 0x244. 20–30 Manufacturer identity code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for Freescale, 0xE IDCODE register ID.
Page 950 NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time of a rising edge of TCK. Figure 35-5. IEEE 1149.1-2001 TAP controller finite state machine MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 951 This allows more rapid movement of test data to and from other components on a board that are required to perform test functions. While the BYPASS instruction is active the system logic operates normally. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 952 This sampling occurs on the rising-edge of TCK in the capture-DR state when the SAMPLE/PRELOAD instruction is active. The sampled data is viewed by shifting it through the boundary scan register to the TDO output MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 953 The e200z0 core OnCE controller supports a complete set of Nexus 1 debug features. A complete discussion of the e200z0 OnCE debug features is available in the e200z0 Reference Manual. 35.9.1 e200z0 OnCE controller block diagram Figure 35-6 is a block diagram of the e200z0 OnCE block. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 954 35-7. The OCMD is updated when the TAP controller enters the update-IR state. It contains fields for controlling access to a resource, as well as controlling single-step operation and exit from OnCE mode. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 955 011 0011 Debug Control Register 2 (DBCR2) 011 0100 – 110 1111 Reserved (do not access) 111 0000 – 111 1001 General Purpose Register Selects [0:9] 111 1010 – 111 1100 Reserved MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 956 To initialize the JTAGC module and enable access to registers, the following sequence is required: 1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS 2. Load the appropriate instruction for the test or action to be performed. MPC5606BK Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor...
Page 957 Appendix A Revision History Appendix A Revision History This appendix describes corrections to the MPC5606BK Microcontroller Reference Manual. For convenience, the corrections are grouped by revision. Changes between revisions 1 and 2 Table A-1. Changes between revisions 1 and 2...
Page 958 Figure 19-1 (XBAR block diagram) to show eDMA as master. Crossbar Switch (XBAR) Table 19-1 (XBAR switch ports for MPC5606BK): • Added row for eDMA • Swapped Logical number and physical master ID Section 19.4, Features, added bullet item for eDMA.
Page 959 Appendix A Revision History Table A-1. Changes between revisions 1 and 2 (continued) Chapter Description Chapter 24, Added Section 24.7.1.5, Overrun. LIN Controller (LINFlexD) Section 24.7.3.2, Identifier filter submode configuration, changed the second sentence to “To configure an identifier filter, the filter must first be activated by setting the corresponding bit in the IFER[FACT] field.”...
Page 960 Appendix A Revision History Table A-1. Changes between revisions 1 and 2 (continued) Chapter Description Chapter 25, Removed references throughout the chapter to “low-cost MCUs.” FlexCAN Removed Note: at end of Section 25.2.2, FlexCAN module features: Note: The individual Rx Mask per Message Buffer feature may not be available in low cost MCUs. Please consult the specific MCU documentation to find out if this feature is supported.
Page 961 Appendix A Revision History Table A-1. Changes between revisions 1 and 2 (continued) Chapter Description Chapter 25, Section 25.5.9.4, Protocol timing, updated the Note following Table 25-22 (Bosch CAN 2.0B FlexCAN (cont.) standard compliant bit time segment settings) to read: “Other combinations of Time Segment 1 and Time Segment 2 can be valid.
Page 962 Appendix A Revision History Table A-1. Changes between revisions 1 and 2 (continued) Chapter Description Chapter 28, Reformatted Table 28-14. Analog-to-Digital Reformatted Table 28-17. Converter (ADC) Reformatted Table 28-24. (Contd..) Reformatted Table 28-29. Reformatted Table 28-31. Reformatted Table 28-33. Reformatted Table 28-35.
Page 963 Appendix A Revision History Table A-1. Changes between revisions 1 and 2 (continued) Chapter Description Chapter 30, Changed reserved area in Table 30-8 from 0x001C – 0x0038 to 0x001C – 0x003B. Flash Memory In the third paragraph of Section 30.4.2.1, CFlash module sectorization, corrected “Bank 0 of the module is divided in 18 sectors “...
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