Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1; Dma Channel X Memory Address Register (Dma_Cmarx) (X = 1; Dma Register Map; Table 41. Dma - Register Map And Reset Values - ST STM32F102 Series Reference Manual

DMA controller (DMA)
9.4.5

DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7)

Address offset: 0x10 + dx20 × Channel number
Reset value: 0x0000 0000
Bits 31:0 PA[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
9.4.6

DMA channel x memory address register (DMA_CMARx) (x = 1 ..7)

Address offset: 0x14 + dx20 × Channel number
Reset value: 0x0000 0000
Bits 31:0 MA[31:0]: Memory Address
Base address of the memory area from/to which the data will be read/written.
9.4.7

DMA register map

The following table gives the DMA register map and the reset values.
Table 41. DMA - register map and reset values
Offset Register
DMA_ISR
0x000
Reset value
DMA_IFCR
0x004
Reset value
DMA_CCR1
0x008
Reset value
DMA_CNDTR1
0x00C
Reset value
DMA_CPAR1
0x010
Reset value 0
DMA_CMAR1
0x014
Reset value 0
0x018
DMA_CCR2
0x01C
Reset value
DMA_CNDTR2
0x020
Reset value
146/690
Reserved
0 0 0 0 0
Reserved
0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0
0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
M
PL PSIZE
SIZE
[1:0] [1:0]
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
M
PL PSIZE
SIZE
[1:0] [1:0]
[1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
RM0008
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0