Figure 13.9 Example Of Stop Condition Issuance Operation Timing In Master Transmit Mode (Mls = Wait = 0) - Renesas H8S/2111B Hardware Manual

SCL
8 9
(master output)
SDA
Bit 0
(master output)
Data 1 [7]
SDA
A
(slave output)
ICDRE
IRIC
IRTR
ICDR
Data 1
User processing [9] ICDR write
Figure 13.9 Example of Stop Condition Issuance Operation Timing
1 2 3
Bit 7 Bit 6 Bit 5 Bit 4
[9] IRIC clear
in Master Transmit Mode (MLS = WAIT = 0)
4 5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
Data 2
Data 2
[11] ACKB read
Rev. 1.00, 05/04, page 313 of 544
Start condition issuance
9
[10]
A
[12] Set BBSY = 1and
SCP = 0
(Stop condition issuance)
[12] IRIC clear