Motorola PowerQUICC II MPC8280 Series Reference Manual page 145

The processor core's exceptions, and conditions that cause them, are listed in Table 2-5.
Exception Vector Offset
Type (hex)
Reserved 00000
System reset 00100
Machine check 00200
DSI 00300
ISI 00400
External 00500
interrupt
Alignment 00600
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Freescale Semiconductor, Inc.
Table 2-5. Exceptions and Conditions
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A system reset is caused by the assertion of either SRESET or HRESET. Note that
the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core
Reference Manual, is determined by the CIP bit in the hard reset configuration word.
This is described in Section 5.4.1, "Hard Reset Configuration Word."
A machine check is caused by the assertion of the TEA signal during a data bus
transaction, assertion of MCP, or an address or data parity error.
The cause of a DSI exception can be determined by the bit settings in the DSISR,
listed as follows:
1 Set if the translation of an attempted access is not found in the primary hash table
entry group (HTEG), or in the rehashed secondary HTEG, or in the range of a
DBAT register; otherwise cleared.
4 Set if a memory access is not permitted by the page or DBAT protection
mechanism; otherwise cleared.
5 Set by an eciwx or ecowx instruction if the access is to an address that is marked
as write-through, or execution of a load/store instruction that accesses a
direct-store segment.
6 Set for a store operation and cleared for a load operation.
11 Set if eciwx or ecowx is used and EAR[E] is cleared.
An ISI exception is caused when an instruction fetch cannot be performed for any of
the following reasons:
• The effective (logical) address cannot be translated. That is, there is a page fault
for this portion of the translation, so an ISI exception must be taken to load the PTE
(and possibly the page) into memory.
• The fetch access is to a direct-store segment (indicated by SRR1[3] set).
• The fetch access violates memory protection (indicated by SRR1[4] set). If the key
bits (Ks and Kp) in the segment register and the PP bits in the PTE are set to
prohibit read access, instructions cannot be fetched from this location.
An external interrupt is caused when MSR[EE] = 1 and the INT signal is asserted.
An alignment exception is caused when the processor core cannot perform a
memory access for any of the reasons described below:
• The operand of a floating-point load or store is to a direct-store segment.
• The operand of a floating-point load or store is not word-aligned.
• The operand of a lmw, stmw, lwarx, or stwcx. is not word-aligned.
• The operand of an elementary, multiple or string load or store crosses a segment
boundary with a change to the direct store T bit.
• The operand of dcbz instruction is in memory that is write-through required or
caching inhibited, or dcbz is executed in an implementation that has either no data
cache or a write-through data cache.
• A misaligned eciwx or ecowx instruction
• A multiple or string access with MSR[LE] set
The processor core differs from MPC603e User's Manual in that it initiates an
alignment exception when it detects a misaligned eciwx or ecowx instruction and
does not initiate an alignment exception when a little-endian access is misaligned.
Chapter 2. G2_LE Core
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Causing Conditions
Exception Model
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