Motorola PowerQUICC II MPC8280 Series Reference Manual page 157

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x10228 Reserved
0x1022C Time counter alarm register (TMCNTAL)
0x10230– Reserved
0x1023F
0x10240 Periodic interrupt status and control register (PISCR)
0x10244 Periodic interrupt count register (PITC)
0x10248 Periodic interrupt timer register (PITR)
0x1024C– Reserved
0x102A8
0x102AA– Reserved
0x1042F
0x10430 Outbound interrupt status register (OMISR)
0x10434 Outbound interrupt mask register (OMIMR)
0x10440 Inbound FIFO queue port register (IFQPR)
0x10444 Outbound FIFO queue port register (OFQPR)
0x10450 Inbound message register 0 (IMR0)
0x10454 Inbound message register 1 (IMR1)
0x10458 Outbound message register 0 (OMR0)
0x1045C Outbound message register 1 (OMR1)
0x10460 Outbound doorbell register (ODR)
0x10468 Inbound doorbell register (IDR)
0x10480 Inbound message interrupt status register (IMISR)
0x10484 Inbound message interrupt mask register (IMIMR)
0x104A0 Inbound free_FIFO head pointer register (IFHPR)
0x104A8 Inbound free_FIFO tail pointer register (IFTPR)
0x104B0 Inbound post_FIFO head pointer register (IPHPR)
0x104B8 Inbound post_FIFO tail pointer register (IPTPR)
0x104C0 Outbound free_FIFO head pointer register (OFHPR)
0x104C8 Outbound free_FIFO tail pointer register (OFTPR)
0x104D0 Outbound post_FIFO head pointer register (OPHPR)
0x104D8 Outbound post_FIFO tail pointer register (OPTPR)
0x104E4 Message unit control register (MUCR)
0x104F0 Queue base address register (QBAR)
MOTOROLA
Freescale Semiconductor, Inc.
Register
PCI
Chapter 3. Memory Map
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Go to: www.freescale.com
R/W Size Reset
— 32 bits —
R/W 32 bits 0x0000_0000 4.3.2.16/-46
— 16 bytes —
R/W 16 bits 0x0000
R/W 32 bits 0x0000_0000 4.3.3.2/-48
R 32 bits 0x0000_0000 4.3.3.3/-49
— 92 bytes —
— 372 bytes —
R/W 32 bits 0x0000_0000 9.12.3.4.3/-84
R/W 32 bits 0x0000_0000 9.12.3.4.4/-85
R/W 32 bits 0x0000_0000 9.12.3.4.1/-83
R/W 32 bits 0x0000_0000 9.12.3.4.2/-83
R/W 32 bits undefined
R/W 32 bits undefined
R/W 32 bits undefined
R/W 32 bits undefined
R/W 32 bits 0x0000_0000 9.12.2.1/-72
R/W 32 bits 0x0000_0000 9.12.2.2/-73
R/W 32 bits 0x0000_0000 9.12.3.4.5/-86
R/W 32 bits 0x0000_0000 9.12.3.4.6/-87
R/W 32 bits 0x0000_0000 9.12.3.2.1/-76
R/W 32 bits 0x0000_0000 9.12.3.2.1/-76
R/W 32 bits 0x0000_0000 9.12.3.2.2/-77
R/W 32 bits 0x0000_0000 9.12.3.2.2/-77
R/W 32 bits 0x0000_0000 9.12.3.3.1/-79
R/W 32 bits 0x0000_0000 9.12.3.3.1/-79
R/W 32 bits 0x0000_0000 9.12.3.3.2/-81
R/W 32 bits 0x0000_0000 9.12.3.3.2/-81
R/W 32 bits 0x0000_0002 9.12.3.4.7/-88
R/W 32 bits 0x0000_0000 9.12.3.4.8/-89
Section/Page
—
—
4.3.3.1/-47
—
—
9.12.1.1/-71
9.12.1.1/-71
9.12.1.2/-71
9.12.1.2/-71
3-5