Motorola PowerQUICC II MPC8280 Series Reference Manual page 161

Table 3-1. Internal Memory Map (continued)
Address
(offset)
0x10D54– Reserved
0x10D5F
0x10D60 Port D data direction register (PDIRD)
0x10D64 Port D pin assignment register (PPARD)
0x10D68 Port D special option register (PSORD)
0x10D6C Port D open drain register (PODRD)
0x10D70 Port D data register (PDATD)
0x10D80 Timer 1 and timer 2 global configuration register
(TGCR1)
0x10D81 Reserved
0x10D84 Timer 3 and timer 4 global configuration register
(TGCR2)
0x10D85– Reserved
0x10D8F
0x10D90 Timer 1 mode register (TMR1)
0x10D92 Timer 2 mode register (TMR2)
0x10D94 Timer 1 reference register (TRR1)
0x10D96 Timer 2 reference register (TRR2)
0x10D98 Timer 1 capture register (TCR1)
0x10D9A Timer 2 capture register (TCR2)
0x10D9C Timer 1 counter (TCN1)
0x10D9E Timer 2 counter (TCN2)
0x10DA0 Timer 3 mode register (TMR3)
0x10DA2 Timer 4 mode register (TMR4)
0x10DA4 Timer 3 reference register (TRR3)
0x10DA6 Timer 4 reference register (TRR4)
0x10DA8 Timer 3 capture register (TCR3)
0x10DAA Timer 4 capture register (TCR4)
0x10DAC Timer 3 counter (TCN3)
0x10DAE Timer 4 counter (TCN4)
0x10DB0 Timer 1 event register (TER1)
0x10DB2 Timer 2 event register (TER2)
0x10DB4 Timer 3 event register (TER3)
MOTOROLA
Freescale Semiconductor, Inc.
Register
CPM Timers
Chapter 3. Memory Map
For More Information On This Product,
Go to: www.freescale.com
R/W Size Reset
— 12 bytes —
R/W 32 bits 0x0000_0000 41.2.3/-3
R/W 32 bits 0x0000_0000 41.2.4/-4
R/W 32 bits 0x0000_0000 41.2.5/-4
R/W 32 bits 0x0000_0000 41.2.1/-2
R/W 32 bits 0x0000_0000 41.2.2/-2
R/W 8 bits 0x00
— 24 bits —
R/W 8 bits 0x00
— 11 bytes —
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
R/W 16 bits 0x0000
Section/Page
—
18.2.2/-4
—
18.2.2/-4
—
18.2.3/-6
18.2.3/-6
18.2.4/-7
18.2.4/-7
18.2.5/-8
18.2.5/-8
18.2.6/-8
18.2.6/-8
18.2.3/-6
18.2.3/-6
18.2.4/-7
18.2.4/-7
18.2.5/-8
18.2.5/-8
18.2.6/-8
18.2.6/-8
18.2.7/-8
18.2.7/-8
18.2.7/-8
3-9