ST STM32G4 Series Reference Manual page 1685

RM0440
37.5.8 Interrupt and status register [alternate] (LPUART_ISR)
Address offset: 0x1C
Reset value: 0x0000 00C0
The same register can be used in FIFO mode enabled (previous section) and FIFO mode
disabled (this section).
FIFO mode disabled
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
Bit 21 TEACK: Transmit enable acknowledge flag
Bit 20 WUF: Wakeup from low-power mode flag
Note: When UESM is cleared, WUF flag is also cleared.
Bit 19 RWU: Receiver wakeup from Mute mode
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
Low-power universal asynchronous receiver transmitter (LPUART)
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. CTS CTSIF
r r
This bit is set/reset by hardware when the Receive Enable value is taken into account by the
LPUART.
It can be used to verify that the LPUART is ready for reception before entering low-power
mode.
kept at reset value.
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the LPUART.
It can be used when an idle frame request is generated by writing TE=0, followed by TE=1
in the LPUART_CR1 register, in order to respect the TE=0 minimum period.
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register.
An interrupt is generated if WUFIE=1 in the LPUART_CR3 register.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value
This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the LPUART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the LPUART_RQR register.
0: Receiver in active mode
1: Receiver in Mute mode
kept at reset value.
24 23 22
Res. Res. REACK TEACK
r
8 7 6
Res. TXE TC RXNE
r r
RM0440 Rev 1
21 20 19 18
WUF RWU SBKF
r r r r
5 4 3 2
IDLE ORE NE
r r r r
17 16
CMF BUSY
r r
1 0
FE PE
r r
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