ST STM32G4 Series Reference Manual page 1676

Low-power universal asynchronous receiver transmitter (LPUART)
Bits 13:12 STOP[1:0]: STOP bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: Reserved.
10: 2 stop bits
11: Reserved
This bitfield can only be written when the LPUART is disabled (UE=0).
Bits 11:5 Reserved, must be kept at reset value.
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the LPUART is disabled (UE=0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.
37.5.4 Control register 3 (LPUART_CR3)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
TXFTCFG[2:0] RXFTIE
rw rw rw
15 14 13
OVRDI
DEP DEM DDRE
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1676/2083
28 27 26 25
RXFTCFG[2:0]
rw rw rw rw
12 11 10 9
Res. CTSIE CTSE
S
rw rw rw
24 23 22
Res. TXFTIE WUFIE
rw rw
8 7 6
RTSE DMAT DMAR
rw rw rw
RM0440 Rev 1
21 20 19 18
WUS[1:0] Res. Res.
rw rw
5 4 3 2
Res. Res. HDSEL Res.
rw
RM0440
17 16
Res. Res.
1 0
Res. EIE
rw