S0: I-Bus; S1: D-Bus; S2: S-Bus; S3, S4: Dma Memory Bus - ST STM32F205 series Reference Manual

RM0033
S0
2.1.1

S0: I-bus

This bus connects the Instruction bus of the Cortex
used by the core to fetch instructions. The target of this bus is a memory containing code
(internal Flash memory/SRAM or external memories through the FSMC).
2.1.2

S1: D-bus

This bus connects the databus of the Cortex
core for literal load and debug access. The target of this bus is a memory containing code or
data (internal Flash memory /SRAM or external memories through the FSMC).
2.1.3

S2: S-bus

This bus connects the system bus of the Cortex
to access data located in a peripheral or in SRAM. Instructions may also be fetch on this bus
(less efficient than ICode). The targets of this bus are the 112 KB & 16 KB internal SRAMs,
the AHB1 peripherals including the APB peripherals, the AHB2 peripherals and the external
memories through the FSMC.
2.1.4

S3, S4: DMA memory bus

This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal SRAM and external memories through the FSMC.

Figure 1. System architecture

ARM GP
Cortex-M3 DMA1
S1 S2 S3
Bus matrix-S
GP MAC
USB OTG
DMA2 Ethernet
HS
S4 S5 S6 S7
M0
M1
M2
M3
M4
M5
M6
®
-M3 core to the BusMatrix. This bus is
®
-M3 to the BusMatrix. This bus is used by the
®
-M3 core to a BusMatrix. This bus is used
RM0033 Rev 8
Memory and bus architecture
ICODE
Flash
memory
DCODE
SRAM
112 Kbyte
SRAM
16 Kbyte
AHB
periph 1
AHB
periph 2
FSMC
Static MemCtl
APB1
APB2
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