S0: Cpu1 I-Bus; S1: Cpu1 D-Bus; S2: Cpu1 S-Bus; S3: Cpu2 S-Bus - ST STM32WL55JC Reference Manual

RM0453
Boot mode selection
1 0
0 0
x 1
1
1
0
x x
1 1
0 1
x 0
1
0
0
x x
1. When engi bytes are invalid or PKA or AES is not available in the product, the SFI/RSS boot firmware installation is not
available.
2. Since CPU1 is kept in hold at reset boot, the system is not able to enter low-power modes (Stop, Standby or Shutdown).
3. Warning: If one of the user options FSD, BRSD, or NBRSD are set to "Security enable" or when RDP is not set to Level 0,
the device must not be boot in SFI/RSS mode.
Values on BOOT0 and BOOT1 are latched after a reset. It is up to the user to provide the
correct value for the required boot mode.
BOOT0 and BOOT1 are also re-sampled when exiting Standby mode. Consequently they
must be kept in the required boot mode. After the startup delay, the CPU1 fetches the top-
of-stack from address 0x0000 0000, then starts code execution from the boot memory at
0x0000 0004.
Depending on the selected boot mode, main Flash memory, system Flash memory and
SRAM1 are accessible as follows:
•
Boot from main Flash memory
The main Flash memory is aliased in the CPU1 boot memory space at address 0x0000
0000 and is also still accessible from its physical address 0x0800 0000. In other words,
Table 1. Device boot mode (continued)
0
0 x
1
0
0
1 Yes
0 x
0 x
1
0
0 x
1
0
0
1 Yes
0 x
0 x
1
RM0453 Rev 2
CPU1 aliasing space
User Flash boot
System Flash boot
Hold
Hold
System Flash boot
SRAM1 boot
User Flash boot
User Flash boot
System Flash boot
Hold
Hold
System Flash boot
SRAM1 boot
User Flash boot
Memory and bus architecture
CPU2 boot
SBRV boot
SBRV boot
(1)(2)(3)
SFI/RSS boot
(2)
SBRV boot
SBRV boot
SBRV boot
SBRV boot
SBRV boot
SBRV boot
(1)(2)(3)
SFI/RSS boot
(2)
SBRV boot
SBRV boot
SBRV boot
SBRV boot
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