Table of Contents
Advertisement
RM0401
7.2.7
SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 8 PVDL: PVD lock
Bit 1 Reserved, must be kept at reset value.
Bit 0 CLL: core lockup lock
7.2.8
Compensation cell control register (SYSCFG_CMPCR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
This bit is set by software. It can be cleared only by a system reset. It enables and
locks the PVD connection to TIM1 Break input. It also locks (write protection) the
PVDE and PVDS[2:0] bits of PWR_CR register.
0: PVD interrupt not connected to TIM1 Break input. PVDE and PVDS[2:0] can be
read and modified
1: PVD interrupt connected to TIM1 Break input. PVDE and PVDS[2:0] are read-only
This bit is set and cleared by software. It enables and locks the LOCKUP (Hardfault)
output of the Cortex-M4 core with TIM1 Break input.
0: Cortex-M4 LOCKUP output not connected to TIM1 Break input
1: Cortex-M4 LOCKUP output connected to TIM1 Break input
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
READY
r
RM0401 Rev 3
System configuration controller (SYSCFG)
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
Res.
PVDL
Res.
CLL
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
3
2
1
0
Res.
Res.
Res.
CMP_PD
rw
159/771
161
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32F410 and is the answer not in the manual?
Questions and answers