Rcc Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr); Rcc Apb1 Peripheral Reset Register For (Rcc_Apb1Rstr) - ST STM32F412 Reference Manual

RM0402
6.3.7

RCC AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIRST: QUADSPI module reset
Set and cleared by software.
0: does not reset QUADSPI module
1: resets QUADSPI module
Bit 0 FSMCRST: Flexible memory controller module reset
Set and cleared by software.
0: does not reset the FSMC module
1: resets the FSMC module
6.3.8

RCC APB1 peripheral reset register for (RCC_APB1RSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
PWR
Res. Res. Res.
RST
15 14 13
SPI3 SPI2
Res. Res.
RST RST
rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 PWRRST: Power interface reset
Set and reset by software.
0: does not reset the power interface
1: resets the power interface
Bit 27 Reserved, must be kept at reset value.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
28 27 26 25
CAN2 CAN1
Res.
RST RST
rw rw rw
12 11 10 9
WWDG
Res. Res.
RST
rw
Reset and clock control (RCC) for STM32F412xx
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
24 23 22
I2CFMP1 I2C3 I2C2
RST RST RST
rw rw rw
8 7 6
TIM14 TIM13 TIM12
RST RST RST
rw rw rw
RM0402 Rev 6
20 19 18
Res. Res. Res.
4 3 2
Res. Res. Res. QSPIRST
21 20 19 18
I2C1 USART3
Res. Res.
RST RST
rw rw
5 4 3 2
TIM7 TIM6 TIM5 TIM4
RST RST RST RST
rw rw rw rw
17 16
Res. Res.
1 0
FSMC
RST
rw rw
17 16
USART2
Res.
RST
rw
1 0
TIM3 TIM2
RST RST
rw rw
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