Motorola PowerQUICC II MPC8280 Series Reference Manual page 138

Programming Model
— Synchronize
• Processor control instructions—These instructions are used for synchronizing
memory accesses and management of caches, TLBs, and the segment registers.
— Move to/from SPR
— Move to/from MSR
— Instruction synchronize
• Memory control instructions—These provide control of caches, TLBs, and segment
registers.
— Supervisor-level cache management
— User-level cache management
— Segment register manipulation
— TLB management
• The G2_LE core implements the following instructions, which are defined as
optional by the PowerPC architecture:
— External Control In Word Indexed (eciwx)
— External Control Out Word Indexed (ecowx)
— Floating Select (fsel)
— Floating Reciprocal Estimate Single-Precision (fres)
— Floating Reciprocal Square Root Estimate (frsqrte)
— Store Floating-Point as Integer Word (stfiwx)
Note that this grouping of the instructions does not indicate which execution unit executes
a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. The PowerPC
architecture uses instructions that are four bytes long and word-aligned. It provides for
byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Floating-point instructions operate on single-precision (one word) and double-precision
(one double word) floating-point operands. It also provides for word and double-word
operand loads and stores between memory and a set of 32 floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a
computation and then modify the same or another memory location, the memory contents
must be loaded into a register, modified, and written back to the target location with
separate instructions. Decoupling arithmetic instructions from memory accesses increases
throughput by facilitating pipelining.
Processors that implement the PowerPC architecture follow the program flow when they
are in the normal execution state. However, the flow of instructions can be interrupted
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