Motorola PowerQUICC II MPC8280 Series Reference Manual page 139

directly by the execution of an instruction or by an asynchronous event. Either kind of
exception may cause one of several components of the system software to be invoked.
2.3.2.3 MPC8280 Implementation-Specific Instruction Set
The G2_LE core instruction set is defined as follows:
• The core provides hardware support for all 32-bit PowerPC instructions.
• The core provides the following two implementation-specific instructions used for
software tablesearch operations following TLB misses:
— Load Data TLB Entry (tlbld)
— Load Instruction TLB Entry (tlbli)
• The G2_LE implements the following instruction, which supports critical interrupts.
This is a supervisor-level, context synchronizing instruction.
— Return from Critical Interrupt (rfci)
2.4 Cache Implementation
The MPC8280 processor core has separate data and instruction caches. The cache
implementation is described in the following sections.
2.4.1 PowerPC Cache Model
The PowerPC architecture does not define hardware aspects of cache implementations. For
example, some processors, including the MPC8280's processor core, have separate
instruction and data caches (Harvard architecture), while others implement a unified cache.
Microprocessors that implement the PowerPC architecture control the following memory
access modes on a page or block basis:
• Write-back/write-through mode
• Caching-inhibited mode
• Memory coherency
The PowerPC cache management instructions provide a means by which the application
programmer can affect the cache contents.
2.4.2 MPC8280 Implementation-Specific Cache
Implementation
As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit
and load/store unit. The surrounding logic selects, organizes, and forwards the requested
MOTOROLA
Freescale Semiconductor, Inc.
Chapter 2. G2_LE Core
For More Information On This Product,
Go to: www.freescale.com
Cache Implementation
2-19