Power Status Register 2 (Pwr_Sr2) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Bit 11 WRFBUSYF: Radio busy wakeup flag

Bits 10:9 Reserved, must be kept at reset value.

Bit 8 WPVDF: Wakeup PVD flag

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 WUF3: Wakeup flag 3

Bit 1 WUF2: Wakeup flag 2

Bit 0 WUF1: Wakeup flag 1

Power status register 2 (PWR_SR2)

This register is partially reset when exiting Standby/Shutdown modes.

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 PVMO3: Peripheral voltage monitoring output: V

Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 PVDO: Power voltage detector output

This bit is set when a wakeup event is detected on radio busy. It is cleared by writing '1' in the

CWRFBUSYF bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on PVD. It is cleared by writing '1' in the

CWPVDF bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by

writing 1 in the CWUF3 bit of the

This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by

writing 1 in the CWUF2 bit of the

This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by

writing 1 in the CWUF1 bit of the

voltage above PVM3 threshold (around 1.62 V)

voltage below PVM3 threshold (around 1.62 V)

PVM3 output is valid after the PVM3 wakeup time.

or voltage level on PVD_IN above the selected PVD threshold

or voltage level on PVD_IN below the selected PVD threshold

PWR status clear register

RM0453 Rev 1

Power control (PWR)

versus 1.62 V

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Power Status Register 2 (Pwr_Sr2) - ST STM32WL5 Series Reference Manual

Power status register 2 (PWR_SR2)

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