Power Status Register 2 (Pwr_Sr2) - ST STM32G0 1 Series Reference Manual

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Bit 8 SBF: Standby flag

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 WUF6: Wakeup flag 6

Bit 4 WUF5: Wakeup flag 5

Bit 3 WUF4: Wakeup flag 4

Bit 2 WUF3: Wakeup flag 3

Bit 1 WUF2: Wakeup flag 2

Bit 0 WUF1: Wakeup flag 1

Power status register 2 (PWR_SR2)

Address offset: 0x14

Reset value: 0x0000 0000. This register is partially reset when exiting Standby/Shutdown

This bit is set by hardware when the device enters Standby mode and is cleared by setting

the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the

system reset.

0: The device did not enter Standby mode

1: The device entered Standby mode

This bit is set when a wakeup event is detected on WKUP6 wakeup pin. It is cleared by

writing 1 in the CWUF6 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP5 wakeup pin. It is cleared by

writing 1 in the CWUF5 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP4 wakeup pin. It is cleared by

writing 1 in the CWUF4 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP3 wakeup pin. It is cleared by

writing 1 in the CWUF3 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP2 wakeup pin. It is cleared by

writing 1 in the CWUF2 bit of the PWR_SCR register.

This bit is set when a wakeup event is detected on WKUP1 wakeup pin. It is cleared by

writing 1 in the CWUF1 bit of the PWR_SCR register.

RM0444 Rev 5

Power control (PWR)

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