Rcc Clock Recovery Rc Register (Rcc_Crrcr); Clock Interrupt Enable Register (Rcc_Cier) - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
Bits 1:0 PLLSRC: PLL input clock source
5.4.5

RCC clock recovery RC register (RCC_CRRCR)

This register applies to STM32G0B1xx and STM32G0C1xx only. It is reserved otherwise.
Address offset: 0x14
Reset value: 0x0000 0000 0000 0000 0000 000x xxxx xxxx
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 HSI48CAL[8:0]: HSI48 clock calibration
5.4.6

Clock interrupt enable register (RCC_CIER)

Address offset: 0x18
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
186/1390
This bit is controlled by software to select PLL clock source, as follows:
00: No clock
01: Reserved
10: HSI16
11: HSE
The bitfield can be written only when the PLL is disabled.
When the PLL is not used, selecting 00 allows saving power.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
These bits are initialized at startup with the factory-programmed HSI48 calibration trim
value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res. Res.
8 7 6
r r r
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res.
RDYIE
RM0444 Rev 5
21 20 19 18
Res. Res. Res.
5 4 3 2
HSI48CAL[8:0]
r r r r
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI HSI48
RDYIE RDYIE RDYIE
rw rw rw rw
RM0444
17 16
Res. Res.
1 0
r r
17 16
Res. Res.
1 0
LSE LSI
RDYIE RDYIE
rw rw