Clock Security System For Lse Clock (Lsecss); Adc Clock; Rtc Clock - ST STM32G0 1 Series Reference Manual

Reset and clock control (RCC)
Note: If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically
generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It
is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the
interrupt clear register
If HSE is selected directly or indirectly (PLLRCLK selected for SYSCLK and HSE selected
as PLL input) as system clock, and a failure of HSE clock is detected, the system clock
switches automatically to HSISYS and the HSE oscillator is disabled. If the HSE clock
(divided or not) is the clock entry of the PLL and PLLRCLK is used as system clock when
the failure occurs, the PLL is disabled, too.
5.2.10

Clock security system for LSE clock (LSECSS)

A clock security system on LSE can be activated by setting the LSECSSON bit in
domain control register
RTC software reset, or after LSE clock failure detection. LSECSSON must be written after
LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY
flags set by hardware), and after selecting the RTC clock by RTCSEL.
The LSECSS works in all modes except VBAT. It keeps working also under system reset
(excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no
longer supplied to the RTC but its registers are not impacted.
Note: If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is
automatically generated. The NMI is executed infinitely unless the LSECSS interrupt
pending bit is cleared. It is therefore necessary that the NMI ISR clears the LSECSSI by
setting the LSECSSC bit in the
If LSE is used as system clock, and a failure of LSE clock is detected, the system clock
switches automatically to LSI. In low-power modes, an LSE clock failure generates a
wakeup. The interrupt flag must then be cleared within the RCC registers.
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by
clearing LSEON), and change the RTC clock source (no clock, LSI or HSE, with RTCSEL),
or take any appropriate action to secure the application.
The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.
5.2.11

ADC clock

The ADC clock is derived from the system clock, or from the PLLPCLK output. It can reach
122 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is
asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This
programmable factor is configured using the CKMODE bitfields in the ADC1_CCR.
If the programmed factor is 1, the AHB prescaler must be set to 1.
5.2.12

RTC clock

The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the
selection cannot be modified without resetting the RTC domain. The system must always be
configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency
for a proper operation of the RTC.
172/1390
(RCC_CICR).
(RCC_BDCR). This bit can be cleared only by a hardware reset or
Clock interrupt clear register
RTC domain control register
RM0444 Rev 5
RTC
(RCC_CICR).
(RCC_BDCR). This
RM0444
Clock