Exti Rising Trigger Selection Register 2 (Exti_Rtsr2); Exti Falling Trigger Selection Register 2 (Exti_Ftsr2) - ST STM32G0 1 Series Reference Manual

Extended interrupt and event controller (EXTI)
Bit 20 FPIF20: Falling edge event pending for configurable line 20
This bit is set upon a falling edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. This bit is cleared by writing 1 into it.
0: No falling edge trigger request occurred
1: Falling edge trigger request occurred
The FPIF20 bit is only available in STM32G0B1xx and STM32G0C1xx. It is reserved in all
the other devices.
Bit 19 Reserved, must be kept at reset value.
Bits 18:0 FPIFx: Falling edge event pending for configurable line x (x = 18 to 0)
Each bit is set upon a falling edge event generated by hardware or by software (through the
EXTI_SWIER1 register) on the corresponding line. Each bit is cleared by writing 1 into it.
0: No falling edge trigger request occurred
1: Falling edge trigger request occurred
The FPIF18 and FPIF17 bits are only available in STM32G071xx and STM32G081xx. They
are reserved in STM32G031xx and STM32G041xx as well as STM32G051xx and
STM32G061xx.
13.5.6

EXTI rising trigger selection register 2 (EXTI_RTSR2)

Address offset: 0x028
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 RT2: Rising trigger event configuration bit of configurable line 34
Bits 1:0 Reserved, must be kept at reset value.
1. The configurable lines are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the configurable line occurs during writing of the register, the associated pending bit is not set.
Rising edge trigger can be set for a line with falling edge trigger enabled. In this case, both edges generate a trigger.
13.5.7

EXTI falling trigger selection register 2 (EXTI_FTSR2)

Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.
328/1390
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit enables/disables the rising edge trigger for the event and interrupt on line 34.
0: Disable
1: Enable
The RT2 bit is only available in STM32G0B1xx and STM32G0C1xx. This bit is reserved in
all the other devices.
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. Res. Res.
RM0444 Rev 5
(1)
.
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. RT2
rw
(1)
RM0444
17 16
Res. Res.
1 0
Res. Res.