System Configuration Controller (Syscfg); Syscfg Registers; Syscfg Configuration Register 1 (Syscfg_Cfgr1) - ST STM32G0 1 Series Reference Manual

System configuration controller (SYSCFG)

8 System configuration controller (SYSCFG)
The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
•
Enabling/disabling I
•
Enabling/disabling the analog switch booster
•
Configuring the IR modulation signal and its output polarity
•
Remapping of some I/O ports
•
Remapping the memory located at the beginning of the code area
•
Flag pending interrupts from each interrupt line
•
Managing robustness feature
8.1

SYSCFG registers

8.1.1

SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations of memory and DMA requests remap and to
control special I/O features.
Two bits are used to configure the type of memory accessible at address 0x0000 0000.
These bits are used to select the physical remap by software and so, bypass the hardware
BOOT selection. After reset these bits take the value selected by the actual boot mode
configuration.
Address offset: 0x00
Reset value: 0x0000 000X (X is the memory mode selected by the actual boot mode
configuration
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
1. Only significant on devices integrating the corresponding peripheral or function, otherwise reserved. Refer to
Availability of peripherals.
248/1390
2
C Fast Mode Plus on some I/O ports
27 26 25
I2C3_
Res. Res. Res.
FMP
11 10 9
UCPD2_ UCPD1_
BOOS
STROBE STROBE
Res.
(1) (1)
w w
RM0444 Rev 5
24 23 22 21
I2C_ I2C_
I2C2_
PA10_ PA9_
(1)
FMP
FMP FMP
rw rw rw rw
8 7 6 5
IR_MOD IR_
TEN [1:0] POL
rw rw rw
20 19 18 17
I2C_ I2C_ I2C_
I2C1_
PB9_ PB8_ PB7_
FMP
FMP FMP FMP
rw rw rw rw
4 3 2 1
PA12_ PA11_ MEM_MODE
Res.
RMP RMP
rw rw rw
Section 1.4:
RM0444
16
I2C_
PB6_
FMP
rw
0
[1:0]
rw