(X = A To F); Gpio Port Bit Reset Register (Gpiox_Brr) (X = A To F) - ST STM32G0 1 Series Reference Manual

General-purpose I/Os (GPIO)
7.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to F)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
AFSEL15[3:0]
rw rw rw
15 14 13
AFSEL11[3:0]
rw rw rw
Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
7.4.11

GPIO port bit reset register (GPIOx_BRR) (x = A to F)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
BR15 BR14 BR13 BR12
w w w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
246/1390
28 27 26 25
AFSEL14[3:0]
rw rw rw rw
12 11 10 9
AFSEL10[3:0]
rw rw rw rw
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
BR11 BR10 BR9
w w w w
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit
24 23 22
AFSEL13[3:0]
rw rw rw
8 7 6
AFSEL9[3:0]
rw rw rw
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
24 23 22
Res. Res. Res.
8 7 6
BR8 BR7 BR6
w w w
RM0444 Rev 5
21 20 19 18
AFSEL12[3:0]
rw rw rw rw
5 4 3 2
AFSEL8[3:0]
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
BR5 BR4 BR3 BR2
w w w w
RM0444
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
BR1 BR0
w w