Cisco MGX 8850 Command Reference Manual page 110

dspclksrcs
Table 2-9
Reason
okay
unknown reason
no clock signal
frequency too high
frequency too low
excessive jitter
missing card or component The active PXM45 has no clock hardware support.
non-existent logical
interface
interface does not support
clocking
phase error
unlockable
out of lock or null
reset—not a valid state
in locking—wideband test
in locking—narrowband
test
locked
When you configure a new clock source or the current clock source changes due to any reason, the
software goes through the process of validating the new, current clock source again. (For example, the
reasons other than direct user-configuration can be: the previous clock source goes out of lock or a
re-synchronization of the clock sources takes place due to a switch-over or a rebuild.) This validation
process takes the current clock source through the following states:
in locking—wideband test
•
in locking—narrowband test
•
• locked
During these states, the node is already using the new clock source as the synchronizing source.
You might also see these states—in the sequence previously listed—if the current clock source was
momentarily lost because it drifted out of the lockable range for either the frequency or the phase. In
such a case, the software goes through one more round of trying to confirm that the current clock source
is lockable before it declares a clock source to be unlockable. If the software finds that, even after this
repeated attempt, that the clock source is not coming back within the lockable range, it declares the clock
Cisco MGX 8850 Routing Switch Command Reference
2-52
Reasons for Change of Clock State
Meaning
The clock source is okay.
The clock manager has no information for Reason.
Loss of signal (LOS) on the clock source.
The frequency has drifted too high.
The frequency has drifted too low
Jitter has exceeded tolerance for this stratum.
The interface is non-existent or not functioning.
The interface does not support clocking.
The clock manger has detected a phase error in the clock.
The clock manager has attempted to lock the source but found
that the clock signal from this source is unlockable.
The clock circuitry is again trying to lock a source that has gone
out of locking range. Note that for Reason, "out of lock" and
"null" is synonymous.
The clock source has been reset.
The clock circuitry is in wide bandwidth mode of the locking
process. In this mode, the circuit tests the integrity of the source
but with wide latitude for frequency accuracy. If the source
passes this test, the circuit proceeds to the narrowband test.
The clock circuitry is in narrow bandwidth locking mode. In this
mode, the circuit stringently tests the integrity of the source.
The clock circuitry is locked to this source.
Chapter 2 Shelf Management Commands
Release 2.0, Part Number 78-10467-04 Rev C0, October 2001