User Manuals: ST PSD4256G6V Programmable Peripherals

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ST PSD4256G6V Manual (127 pages)

Flash in-system programmable (ISP) peripherals for 8-bit or 16-bit MCUs

Brand: ST | Category: Microcontrollers | Size: 1 MB

Table of Contents
2
Description
11
In-System Programming (ISP) Via JTAG
11
First Time Programming
11
Inventory Build-Up of Pre-Programmed Devices
11
Expensive Sockets
11
In-Application Programming
12
Simultaneous Read and Write to Flash Memory
12
Complex Memory Mapping
12
Separate Program and Data Space
12
Psdsoft
12
Table 1. Pin Names
13
Figure 1. Logic Diagram
13
Figure 2. LQFP80 Connections
14
Table 2. LQFP80 Pin Description
16
Figure 3. PSD Block Diagram
19
PSD Architectural Overview
20
Memory
20
Plds
20
I/O Ports
20
MCU Bus Interface
21
ISP Via JTAG Port
21
In-System Programming (ISP)
21
In-Application Programming (IAP)
21
Table 3. PLD I/O
21
Table 4. JTAG Signals on Port E
21
Page Register
22
Power Management Unit (PMU)
22
Table 5. Methods of Programming Different Functional Blocks of the PSD
22
Development System
23
Figure 4. Psdsoft Development Tool
24
PSD Register Description and Address Offsets
25
Table 6. Register Address Offset
25
Register Bit Definition
27
Table 7. Data-In Registers - Ports A, B, C, D, E, F, and G
27
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, and G
27
Table 9. Direction Registers - Ports A, B, C, D, E, F, and G
27
Table 10. Control Registers - Ports E, F, and G
27
Table 11. Drive Registers - Ports A, B, D, E, and G
27
Table 12. Enable-Out Registers - Ports A, B, C, and F
27
Table 13. Input Macrocells - Ports A, B, and C
27
Table 14. Output Macrocells a Register
28
Table 15. out Macrocell B Register
28
Table 16. Mask Macrocell a Register
28
Table 17. Mask Macrocell B Register
28
Table 18. Flash Memory Protection Register 1
28
Table 19. Flash Memory Protections Register 2
28
Table 20. Flash Boot Protection Register
28
Table 21. JTAG Enable Register
29
Table 23. PMMR0 Register
29
Table 24. PMMR2 Register
29
Table 25. VM Register
30
Table 26. Memory_Id0 Register
30
Detailed Operation
31
Memory Blocks
31
Table 28. Memory Block Size and Organization
31
Primary Flash Memory and Secondary Flash Memory Description
32
Memory Block Select Signals
32
Ready/Busy (PE4)
32
Memory Operation
33
Table 29. 16-Bit Instructions
35
Instructions
36
Power-Up Condition
36
Read
37
READ Memory Contents
37
READ Primary Flash Identifier
37
READ Memory Sector Protection Status
37
Reading the Erase/Program Status Bits
37
Table 30. 8-Bit Instructions
37
Table 31. Status Bits
37
Data Polling (DQ7) - DQ15 for Motorola
38
Toggle Flag (DQ6) - DQ14 for Motorola
38
Error Flag (DQ5) - DQ13 for Motorola
39
Erase Time-Out Flag (DQ3) - DQ11 for Motorola
39
Programming Flash Memory
40
Data Polling
40
Data Toggle
41
Figure 5. Data Polling Flowchart
41
Unlock Bypass
42
Figure 6. Data Toggle Flowchart
43
Erasing Flash Memory
44
Flash Bulk Erase
44
Flash Sector Erase
44
Suspend Sector Erase
45
Resume Sector Erase
45
Specific Features
46
Flash Memory Sector Protect
46
RESET Instruction
46
Reset (RESET) Pin
46
Sram
47
Memory Select Signals
48
Example
48
Memory Select Configuration for Mcus with Separate Program and Data Spaces
48
Configuration Modes for Mcus with Separate Program and Data Spaces
49
Separate Space Modes
49
Combined Space Modes
49
80C31 Memory Map Example
49
Figure 7. Priority Level of Memory and I/O Components
49
Figure 8. 8031 Memory Modules - Separate Space
50
Figure 9. 8031 Memory Modules - Combined Space
50
Page Register
51
Figure
51
Memory ID Registers
52
Table 27. Memory_Id1 Register
52
Plds
53
Table 32. DPLD and CPLD Inputs
53
Figure 11. PLD Diagram
54
Decode PLD (DPLD)
55
Figure 12. DPLD Logic Array
55
Complex PLD (CPLD)
56
Output Macrocell (OMC)
57
Figure 13. Macrocell and I/O Port
57
Product Term Allocator
58
Table 33. Output Macrocell Port and Data Bit Assignments
58
Loading and Reading the Output Macrocells (OMC)
59
The OMC Mask Register
59
The Output Enable of the OMC
59
Input Macrocells (IMC)
60
Figure 14. CPLD Output Macrocell
60
External Chip Select
61
Figure 15. Input Macrocell
61
Figure 16. External Chip Select Signal
62
Figure 17. Handshaking Communication Using Input Macrocells
62
MCU Bus Interface
63
Table 34. 16-Bit Mcus and Their Control Signals
63
Table 35. 8-Bit Mcus and Their Control Signals
63
PSD Interface to a Multiplexed Bus
64
Figure 18. an Example of a Typical Multiplexed Bus Interface
64
PSD Interface to a Non-Multiplexed, 16-Bit Bus
65
Data Byte Enable Reference for a 16-Bit Bus
65
Table 36. 16-Bit Data Bus with BHE
65
Figure 19. an Example of a Typical Non-Multiplexed Bus Interface
65
16-Bit MCU Bus Interface Examples
66
Table 37. 16-Bit Data Bus with WRH and WRL
66
Table 38. 16-Bit Data Bus with SIZ0, A0 (Motorola MCU)
66
Table 39. 16-Bit Data Bus with LDS, UDS (Motorola MCU)
66
80C196 and 80C186
67
Figure 20. Interfacing the PSD with an 80C196
67
Mc683Xx and MC68HC16
68
Figure 21. Interfacing the PSD with an MC68331
68
80C51Xa
69
Figure 22. Interfacing the PSD with an 80C51XA-G3
69
Figure 23. Interfacing the PSD with an H83/2350
70
Mmc2001
71
Figure 24. Interfacing the PSD with an MMC2001
72
C16X Family
73
Figure 25. Interfacing the PSD with a C167CR
73
8-Bit MCU Bus Interface Examples
74
80C31
74
Figure 26. Interfacing the PSD with an 80C31
74
80C251
75
Page Mode
75
Non
75
Table 40. 80C251 Configurations
75
Figure 27. Interfacing the PSD with the 80C251, with One READ Input
76
Figure 28. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
76
80C51Xa
77
Figure 29. Interfacing the PSD with the 80C51XA, 8-Bit Data Bus
77
68Hc11
78
Figure 30. Interfacing the PSD with a 68HC11
78
I/O Ports
79
General Port Architecture
79
Port Operating Modes
80
Figure 31. General I/O Port Architecture
80
MCU I/O Mode
81
PLD I/O Mode
81
Address out Mode
81
Table 41. Port Operating Modes
82
Table 42. Port Operating Mode Settings
82
Address in Mode
83
Data Port Mode
83
Peripheral I/O Mode
83
Table 43. I/O Port Latched Address Output Assignments
83
JTAG In-System Programming (ISP)
84
MCU RESET Mode
84
Port Configuration Registers (PCR)
84
Figure 32. Peripheral I/O Mode
84
Control Register
85
Direction Register
85
Drive Select Register
85
Table 44. Port Configuration Registers (PCR)
85
Table 45. Port Pin Direction Control, Output Enable P.T. Not Defined
85
Port Data Registers
86
Data in
86
Data out Register
86
Table 46. Port Pin Direction Control, Output Enable P.T. Defined
86
Table 47. Table
86
Table 49. Table
86
Output Macrocells (OMC)
87
Mask Macrocell Register
87
Input Macrocells (IMC)
87
Enable out
87
Ports A, B and C - Functionality and Structure
88
Figure 33. Port A, B, and C Structure
88
Port D - Functionality and Structure
89
Figure 34. Port D Structure
89
Port E - Functionality and Structure
90
Port F - Functionality and Structure
90
Port G - Functionality and Structure
90
Figure 35. Port E, F, and G Structure
91
Power Management
92
Automatic Power-Down (APD) Unit and Power-Down Mode
93
Power-Down Mode
93
Table 50. Effect of Power-Down Mode on Ports
93
Other Power Saving Options
94
PLD Power Management
94
Table 51. PSD Timing and Standby Current During Power-Down Mode
94
Figure 36. APD Unit
94
PSD Chip Select Input (CSI, PD2)
95
Input Clock
95
Figure 37. Enable Power-Down Flowchart
95
Input Control Signals
96
Table
96
RESET Timing and Device Status at RESET
97
Power-On RESET
97
Warm RESET
97
I/O Pin, Register and PLD Status at RESET
97
RESET of Flash Memory Erase and Program Cycles
97
Figure 38. Reset (RESET) Timing
97
Table 53. Status During Power-On RESET, Warm RESET, and Power-Down Mode
98
In-Circuit Programming Using the Serial Interface
99
Standard JTAG Signals
99
JTAG Extensions
100
Security and Flash Memory Protection
100
Initial Delivery State
102
Maximum Rating
103
Table 55. Absolute Maximum Ratings
103
DC and AC Parameters
104
Figure 39. PLD ICC / Frequency Consumption
104
CC = 3.0 V (with Turbo Mode On)
105
CC = 3.0V (with Turbo Mode Off)
106
Table 58. Operating Conditions
107
Table 59. AC Signal Letters for PLD Timing
107
Table 60. AC Signal Behavior Symbols for PLD Timing
107
Table 61. AC Measurement Conditions
107
Table 62. Capacitance
108
Figure 40. AC Measurement I/O Waveform
108
Figure 41. AC Measurement Load Circuit
108
Figure 42. Switching Waveforms - Key
108
Table 63. DC Characteristics
109
Table 64. CPLD Combinatorial Timing
110
Figure 43. Input to Output Disable / Enable
110
Figure 44. Asynchronous RESET / Preset
110
Figure 45. Synchronous Clock Mode Timing - PLD
110
Table 65. CPLD Macrocell Synchronous Clock Mode Timing
111
Table 66. CPLD Macrocell Asynchronous Clock Mode Timing
111
Figure 46. Asynchronous Clock Mode Timing (Product Term Clock)
111
Table 67. Input Macrocell Timing
113
Figure 47. Input Macrocell Timing (Product Term Clock)
113
Table 68. READ Timing
114
Figure 48. READ Timing Diagram
114
Table 69. WRITE Timing
116
Figure 49. WRITE Timing Diagram
116
Table 70. Port F Peripheral Data Mode READ Timing
118
Figure 50. Peripheral I/O READ Timing Diagram
118
Table 71. Port F Peripheral Data Mode WRITE Timing
119
Table 72. Program, WRITE and Erase Times
119
Figure 51. Peripheral I/O WRITE Timing Diagram
119
Table 73. Reset (RESET) Timing
120
Table 74. Power-Down Timing
120
Figure 52. Reset (RESET) Timing Diagram
120
Table 75. ISC Timing
121
Figure 53. ISC Timing Diagram
121
Package Mechanical Information
122
Figure 54. LQFP80 - 80-Lead Plastic Thin, Quad, Flat Package Outline
122
Table 76. LQFP80 - 80-Lead Plastic Thin, Quad, Flat Package Mechanical Data
123
Part Numbering
124
Table 77. Ordering Information Scheme
124
Appendix A Pin Assignments
125
Table 78. LQFP80 Pin Connections
125
Revision History
126
Table 79. Document Revision History
126

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User Manuals: ST PSD4256G6V Programmable Peripherals

ST PSD4256G6V Manual (127 pages)

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