Memory And Bus Architecture; System Architecture; Figure 1. Low And Medium Density Value Line System Architecture - ST STM32F100 Series Reference Manual

Memory and bus architecture

2 Memory and bus architecture
2.1

System architecture

In low-and medium-density value line devices, the main system consists of:
•
Three masters:
–
–
•
Three slaves:
–
–
–
These are interconnected using a multilayer AHB bus architecture as shown in
Cortex-M3
DMA1
Ch.1
Ch.2
Ch.7
34/709
®
Cortex -M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 (general-purpose DMA)
Internal SRAM
Internal flash memory
AHB to APB bridges (AHB to APBx), which connect all the APB peripherals

Figure 1. Low and medium density value line system architecture

ICode
DCode
Sys tem
DMA
FLASH
(Flash
interface)
Bridge 1
AHB system bus
Bridge 2
Reset & clock
control (RCC)
DMA request
RM0041 Rev 6
Flash
memory
SRAM
APB2
TIM17
GPIO
SPI2
DAC2
TIM16
TIM7
DAC1
TIM15 TIM6
I2C2
TIM4
USART1 I2C1
TIM3
USART3
SPI1
TIM2
USART2
TIM1
ADC1
DMA request
ai17302
RM0041
Figure 1.
APB1
CEC