Memory And Bus Architecture; System Architecture - ST STM32F207 Series Reference Manual

Memory and bus architecture

2 Memory and bus architecture
2.1

System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
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Height masters:
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Seven slaves:
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in
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®
Cortex -M3 core I-bus, D-bus and S-bus
DMA1 memory bus
DMA2 memory bus
DMA2 peripheral bus
Ethernet DMA bus
USB OTG HS DMA bus
Internal Flash memory ICode bus
Internal Flash memory DCode bus
Main internal SRAM1 (112 KB)
Auxiliary internal SRAM2 (16 KB)
AHB1peripherals including AHB to APB bridges and APB peripherals
AHB2 peripherals
FSMC
Figure 1.
RM0033 Rev 9
RM0033