Flash Status Register (Flash_Sr) - ST STM32F205 Programming Manual

Flash memory interface
2.8.4

Flash status register (FLASH_SR)

The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
15 14 13 12
Reserved
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
Flash memory operation and cleared when the operation finishes or an error occurs.
Bits 15:8 Reserved, must be kept cleared.
Bit 7 PGSERR: Programming sequence error
Bit 6 PGPERR: Programming parallelism error
Bit 5 PGAERR: Programming alignment error
Bit 4 WRPERR: Write protection error
22/29
27 26 25
11 10 9
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Set by hardware when a write access to the Flash memory is performed by the code while
the control register has not been correctly configured.
Cleared by writing 1.
Set by hardware when the size of the access (byte, half-word, word, double word) during the
program sequence does not correspond to the parallelism configuration PSIZE (x8, x16,
x32, x64).
Cleared by writing 1.
Set by hardware when the data to program cannot be contained in the same 128-bit Flash
memory row.
Cleared by writing 1.
Set by hardware when an address to be erased/programmed belongs to a write-protected
part of the Flash memory.
Cleared by writing 1.
24 23 22
Reserved
8 7 6
PGSERR PGPERR PGAERR WRPERR
rc_w1 rc_w1 rc_w1
DocID15687 Rev 5
21 20 19 18
5 4 3
Reserved
rc_w1
PM0059
17 16
BSY
r
2 1 0
OPERR EOP
rc_w1 rc_w1